Assume the following design parameters for the circuit shown below (nominal VDD-

Question

Assume the following design parameters for the circuit shown below (nominal VDD-1.2V): intrinsic delay of NAND cell 100ps VDD-1.2V, intrinsic delay of INVERTER cell 40ps VDD-1.2V PMOS leakage is 1 pA IV 0V NMOS leakage is 3pA Vgs 0V PMOS and NMOS IVth- 0.4V velocity saturation factor 1 average equivalent input capacitance of NAND cell is 5fF average equivalent input capacitance of INVERTER cell is 3fF average equivalent input capacitance of FFs is 5fF neglect wiring and cell output capacitances List the cells that integrate the critical path of this design correctly? Yes or no 3 What is the energy required by cell 1 to make an output transition from 0 1. 4 What is the leakage of cell 1 if its input signal is a logical 0? 5 What is the relative leakage reduction of the NMOS transistors if 1V RBB is applied? Determine the static power consumption of the circuit for the input vector ABC-100 (do not consider FF)

Explanation / Answer

Solution:

1) The critical path is the one having highest delay of all the paths from input to output which produce valid logic expression.

so here as we don't know the setup,hold,tcq values of registers,we compute only combinational path

paths contributing by all cells from input to output is:

a. 1-4-6 = 40+100+40 = 180 ps

b. 2-4-6 = 100+100+40 = 240 ps

c. 2-5-7 = 100+100+100 = 300 ps

d. 1-5-7 = 40+100+100 = 240 ps

hence the critical path is =  2-5-7

2) Yes , it will operate for the clock period of 500 ps

because the critical path delay is less than clock and also set-up , hold time ,clock to q time of register are very small values so it will operate properly.

3) The energy required by cell 1 to go from 0 to1 is equivalent to charge the inverter capacitor for the rise time of the delay is = (1/2) CVDD2

= (1/2) x 3 x 10-12 x 1.2 V = 1.8 pJ

4) The inverter is made up of NMOS and PMOS connected with PMOS as pull up device and NMOS as pull down device so when input signal is logical 0 then PMOS is on and NMOS is off.

so the leakage will be the leakage of PMOS device which is equal to 1pA .

5) when 1 V is applied to the NMOS the device starts conducting and leakage of 3 pA will not be there as long as the device is on.

Related Questions

Navigate

• Browse (All)
• Browse A
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.