This module will generate a random number using a 16-bit counter and the input s

Question

This module will generate a random number using a 16-bit counter and the input sample (which shall be connected to KEY[0] n the top level design.) This module shall have a free running 16-bit counter that increments each clock cycle. When sample transitions from high to low (KEY[0] is pressed), the contents of the counter should be saved to the lower 16-bits of a 32-bit register. When sample then transitions from low to high (KEY[0] is released), the contents of the counter should be saved to the upper 16-bits of the 32-bit register. Based off the timing of the pressing and releasing KEY[0], a random 32-bit number will be generated in the register. This module also has a debug[1: 0] input which selects between routing the random number to the output, or known prime/composite numbers. This will be helpful for debugging your system. The expected behavior of this is given in the following Table.

Explanation / Answer

module 16bitcounter(clk,hold,reset,q);
input clk,hold,reset;
output [15:0]q;
reg [15:0]q;
initial q=15'b0000000000000000;
always @(posedge clk)
begin
if (reset)
q=15'b0000000000000000;
else if (hold)
q=q;
else
q=q+1;
end
endmodule

module numbergen(clk,debug,KEY,value);
input [1:0]debug;
input KEY;
input clk;
output [31:0]value;
wire [15:0]tmp1;
reg [31:0]tmp2;
16bitcounter count1(clk,0,0,tmp1);
always @(posedge KEY)
begin
tmp2[31:16] = tmp1[15:0];
end
always @(negedge KEY)
begin
tmp2[15:0] = tmp1[15:0];
end

case (debug)
2'b00 : value[31:0]=tmp2[31:0];
2'b01 : value[31:0]=32'b10101110000111000101011000001110;
2'b10 : value[31:0]=32'b00000000000000000000000001001111;
2'b11 : value[31:0]=32'b01111111111111111111111111111111;
endcase
endmodule

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