The logic for a Full-Adder (FA) (from the lecture notes) is shown in the figure

Question

The logic for a Full-Adder (FA) (from the lecture notes) is shown in the figure below. Three logic gates are used in the implementation: INV, 2-input NAND, and OAI (OR-AND-INV-push the bubbles will reveal the reason for the name). INV delay is Ins and NAND delay is 2ns for either input. The OAI gate has 2 possible delays, for the NAND input, the delay is 1.5ns (note the difference with a 2-input NAND logic gate), and for the OR input, the delay is 3ns. (a) Determine the contamination delay (min) for t_c_a2cout, t_c_a2s. (b) Determine the propagation delay (max) for td_a2cout, t_d_a2s. (c) For a ripple carry adder of 4 bits, determine the contamination and propagation delay for t_c_cin(0)2cout[3] and t_d_cin[0]2cout[3] where cin[0] is the carry in of the 00 bit and cout[3] is the carry out of the 3^rd bit. (d) If the ripple carry adder of (c) is used in a datapath for one stage of a pipeline, what is the minimum cycle time? Assume that the DFF has a t_setup of 0.5ns and t_d_CQ of 1ns. (e) If instead of the design in (d), each bit adder is in its own stage of a pipeline, what is the minimum cycle time. (f) For the design in (e), what is the hold-time requirement to not violate timing. Note that the DFF has a t_c_CQ of 0.5ns.

Explanation / Answer

Solution:

A ) Contamination delay:

Identifying the shortest path of contamination delays from input to the output determines the contamination dalay of the path.

Here, contamination delay and propagation delay are not given seperately so,we consider for each gate,

contamination delay (tcd) = propagation delay (tpd)

for INV = tcd = tpd = 1 ns

for NAND = tcd = tpd = 2 ns

in OAI , NAND = tcd =tpd = 1.5 ns and OR= tcd =tpd = 3 ns

A) # Calculation of Contamination delay:

a) tc_a2cout = the path is = a -NAND- g' - OR - Cout ... minimum path

= 2 ns + 3 ns = 5 ns

b) tc_a2s = There are two paths, we will decide with minimum dalay path

path 1 = a - OAI gate - p' - NAND - OR - s = 1.5 + 3 + 2 + 3 = 9.5 ns

path 2 = a - g' - OR - p' - NAND - OR - s = 2 + 3 + 2 + 3 = 10 ns

so the contamination delay is the minimum path delay so

tc_a2s = 9.5 ns

B) # Calculation of propagation delay:

Identifying the longest path of propagation from input to the output determines the propagation

dalay of the path.

a) td_a2cout

path1 = a - NAND - OR with inverted inputs - AND with inverted inputs - OR ....is the longest one

= 2 + 3 + 1.5 + 3 = 9.5 ns

path2 = a - AND with inverted inputs - OR with inverted inputs - AND with inverted inputs - OR with inverted inputs

= 1.5 + 3 + 1.5 + 3 = 9 ns

so the longest path delay is the propagation delay hence,

td_ a2cout = 9.5 ns

b) td_ a2s

there are four paths and we have to find maximum delay path here,

path1 = a - NAND-OR with inverted inputs-NAND-OR with inverted inputs = 2 + 3 + 2 + 3 =10 ns

path2 = a-NAND-OR with inverted inputs-AND with inverted inputs-OR with inverted inputs=2+ 3 + 1.5 + 3 = 9.5 ns

path3 = a-AND with inverted inputs-OR with inverted inputs- NAND- OR with inverted inputs = 1.5 +3+2 +3 =9.5 ns

path4 = a-AND with inverted inputs-OR with inverted inputs-AND with inverted inputs-OR with inverted inputs

= 1.5+3+1.5+3 =9 ns

Hence,The propagation delay td_a2s = 10 ns

C) # 4-Bits Ripple carry adder contamination and propagation delay:

In 4-bit ripple carry adder , carry passes from first adder to the last adder and as there are 4 adders

The total contamination delay will be the sum of 4 adders = 4 x  tc_a2cout = 4 x 5 ns = 20 ns

hence, tc_cin(0)2cout(3) = 20 ns

The total propagation delay will be summation of all 4 adders = 4 x td_ a2cout = 4 x 9.5 ns = 38 ns

hence, td_cin(0)2cout(3) = 38 ns

D) The minimum cycle time will be the propagation delay of one adder

Here, D-ffs are added in the design to make efficient pipeline structure so tcq from the previous one and tset-up of the next D-ff is added to this delay to find the minimum path to determine the clock period

So , the minimum cycle time is = tc-q + td_a2s + tset-up = 1 ns + 10ns + 0.5 = 11.5 ns

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