A particular processor has a set of instructions that we might use to perform bi

Question

A particular processor has a set of instructions that we might use to perform bitwise operations:

It can perform a Load Immediate (LDI) instruction that places an immediate (or constant) value into a register. The first operand is the destination register. The second operand is the immediate value that we want to place into the register. For example, the instruction shown below places the binary value 00110011 into register R1:

LDI(R1, 00110011)

It can perform the AND, OR, and XOR operators on two register operands, and store the result into a destination register. For example, the instruction shown below ANDs the contents of registers R1 and R2 (whatever they might be) and places the result into R3:

AND(R3, R1, R2)

Using these instruction, we can write short programs to perform bitwise instructions by first putting an immediate value into a register, and then performing a logic operator on two register values. For example, if we want to AND the value in R2 with the immediate value 00110011 and store the result into R3, we can put the immediate value into R1, and then AND R1 and R2 and place the result into R3. The sequence of operations to do those two things looks like this:

LDI(R1, 00110011)

AND(R3, R1, R2)

Using notation similar to that shown above, indicate how a user might carry out the following tasks:

1- Register R1 contains a value, but the only relevant bits to a particular operation are in bit positions 3, 2, 1, and 0 of R1. Thus, we want to keep those bits while making the other bits equal 0. The result of the operation should be placed the result into R3. (You may choose any other register to hold the bitmask.)

(Think about this operation carefully. This processor has a regular AND operation. Which bit value of the mask will do the job of maintaining the corresponding bit value of the operand? Which one will do the job of “not maintaining” the corresponding bit value of the operand?)

2- Register R4 contains a value. We wish to place a value into register R5 so that we can use the value to enable a peripheral. To correctly enable the device, the value that ends up in R5 needs to equal the value in R4, except that the bits in positions 7, 5, 3, and 1 of R4 must be set; the bits in the remaining positions must remain unchanged. (You may choose any other register to hold the bitmask.)

3- Now that the value is in R5, we want to change the status of the peripheral. Thus, we must complement the values in bit positions 6, 5, 3, and 0; the bits in the remaining positions must remain unchanged. The result should end up in R5. (You may choose any other register to hold the bitmask.)

In each case, you don’t know what value is in the source register operand. You only know that it needs to be changed in the way described in each part of this problem.

Explanation / Answer

1) Instruction sequence:

LDI(R6,00001111)

AND(R3, R6, R1)

-------------------------------------------

Explanation:

For maintaining the lower half of R1, we need to fill up the lower 4 bits of the bitmask with 1s. The upper 4 bits(i.e from position 4 to7) of the bit mask will be set to 0. This is done because we know that if any bit is bitwise AND'ed with 1, it results in getting the same bit. But bitwise AND'ing with 0 will always give us 0. So by using the bit mask 00001111, that is stored in R6, we are preserving the bits 3,2,1,0 in R1. In the second instruction, AND operation is performed between R1 and R6, and the result is stored in R3.

2) ----------------------------------

LDI (R6,01010101)

AND (R5, R6, R4)

-------------------------------------

Explanation:

For dropping the bits 7,5,4,3 and 1 from R4, the bitmask stored in R6 contains 0's in those positions. Thus, by carrying out an AND operation between the R4 and R6, we get our desired result and store in the destination register R5.

3)

-------------------------------------

LDI(R6,01010101)

XOR(R5, R6, R5)

-----------------------------------

Explanation:

When a bit is bitwise XOR'ed, then the bit is complemented. But to ignore or pass other bits, we only need to XOR them with 0's. Therefore, in order to complement the positions 6,4,2 and 0, we have placed 1 in the respective positions of the bitmask. Thus, by XOR'ing R5 with 0x55 we get our desired result.

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