Academic Integrity: tutoring, explanations, and feedback — we don’t complete graded work or submit on a student’s behalf.

1. Design a circuit that can perform simple arithmetic and logical instructions

ID: 2085195 • Letter: 1

Question

1. Design a circuit that can perform simple arithmetic and logical instructions using VHDL and an eSOC board.

   a. Design and simulate a 4-bit, 8-function ALU to implement the operations shown in Figure 6.1

b. Copy and paste your VHDL program.

Design and simulate a 4-bit, 8-function ALU to implement the operations shown in Figure 0.l F2 F1 F0 Output Function Output A Input Output = A Complement Output = A Plus B Output = A Minus B S4 -- SO S-A S=NOT A S=A+B S-A B 0 ut=AAND B ut=AOR B ut Increment A S=AB S=A+1 S-A-1 0 Output Decrement A

Explanation / Answer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity alu_8bit is
Port ( A : in signed(3 downto 0);
        B : in signed(3 downto 0);
        F : in STD_LOGIC_VECTOR (2 downto 0);
        S : out signed(3 downto 0));
end alu;

architecture Behavioral of alu_8bit is
begin
process(A, B, F)
begin
case F is
when "000" =>
S <= A ; -- A input
when "001" =>
S <= not A ; --NOT A
when "010" =>
S <= A + B; --A + B
when "011" =>
S <= A - B; --A - B
when "100" =>
S <= A and B; --A AND B
when "101" =>
S <= A or B; --A OR B
when "110" =>
S <= A + 1 ; --NOT gate
when "111" =>
S <= A - 1 ; --XOR gate
when others =>
NULL;
end case;

end process;

end Behavioral;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY Tb_alu IS
END Tb_alu;

ARCHITECTURE behavior OF Tb_alu IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT alu_8bit
PORT(
A : IN signed(3 downto 0);
B : IN signed(3 downto 0);
F : IN std_logic_vector(2 downto 0);
S : OUT signed(3 downto 0)
);
END COMPONENT;

--Inputs
signal A : signed(3 downto 0) := (others => '0');
signal B : signed(3 downto 0) := (others => '0');
signal F : std_logic_vector(2 downto 0) := (others => '0');

--Outputs
signal S : signed(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP (
A => A,
B => B,
F => F,
S => S
);

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

-- insert stimulus here

A <= "1001";
B <= "1111";

F <= "000";
wait for 100 ns;
F <= "001";
wait for 100 ns;
F <= "010";
wait for 100 ns;
F <= "011";
wait for 100 ns;
F <= "100";
wait for 100 ns;
F <= "101";
wait for 100 ns;
F <= "110";
wait for 100 ns;
F <= "111";
end process;

-- report changes of the interrupt signal

END;