Verilog – generate and simulate a logic gate Each student will be assigned a log
ID: 2085640 • Letter: V
Question
Verilog – generate and simulate a logic gate
Each student will be assigned a logic cell to simulate. Each will have 5 inputs and 1 output.
The assignment is:
1. Write a rtl module of your cell with inputs a,b,c,d,e and output z
a. This should be in file “OA311_rtl.v” { (a+b+d)de }
2. generate a test bench in a file called “OA311_test.v” for the cell including
i. a monitor statement for the inputs and output along with the appropriate header.
ii. Verilog dump file called “Module_name.vcd”.
iii. Be sure you have covered all 32 of the input/output states of the cell.
iv. Include a call to your behavioral cell
3. Simulate the cell and verify it has the correct function
4. Write a gate level description of the cell using the supplied library (AND2/OR2/INV gates) and call it “AO311.v”. DO NOT MODIFY THE LIBRARY
5. Modify behavioral test bench to include both the behavioral and gate model and overwrite (you may want to copy the original) the file called “OA311_test.v and verify that matches the behavioral module
a. Inputs may be the same for the behavioral and gate level models
b. Outputs MUST have different names – using the same name would short them together.
c. Add the gate outputs to the monitor and header statements
Explanation / Answer
3. Output
A=0 B=0 C=0 D=0 E=0
output of bool_logic Z=0
A=0 B=0 C=0 D=0 E=1
output of bool_logic Z=0
A=0 B=0 C=0 D=1 E=0
output of bool_logic Z=0
A=0 B=0 C=0 D=1 E=1
output of bool_logic Z=1
A=0 B=0 C=1 D=0 E=0
output of bool_logic Z=0
A=0 B=0 C=1 D=0 E=1
output of bool_logic Z=0
A=0 B=0 C=1 D=1 E=0
output of bool_logic Z=0
A=0 B=0 C=1 D=1 E=1
output of bool_logic Z=1
A=0 B=1 C=0 D=0 E=0
output of bool_logic Z=0
A=0 B=1 C=0 D=0 E=1
output of bool_logic Z=0
A=0 B=1 C=0 D=1 E=0
output of bool_logic Z=0
A=0 B=1 C=0 D=1 E=1
output of bool_logic Z=1
A=0 B=1 C=1 D=0 E=0
output of bool_logic Z=0
A=0 B=1 C=1 D=0 E=1
output of bool_logic Z=0
A=0 B=1 C=1 D=1 E=0
output of bool_logic Z=0
A=0 B=1 C=1 D=1 E=1
output of bool_logic Z=1
A=1 B=0 C=0 D=0 E=0
output of bool_logic Z=0
A=1 B=0 C=0 D=0 E=1
output of bool_logic Z=0
A=1 B=0 C=0 D=1 E=0
output of bool_logic Z=0
A=1 B=0 C=0 D=1 E=1
output of bool_logic Z=1
A=1 B=0 C=1 D=0 E=0
output of bool_logic Z=0
A=1 B=0 C=1 D=0 E=1
output of bool_logic Z=0
A=1 B=0 C=1 D=1 E=0
output of bool_logic Z=0
A=1 B=0 C=1 D=1 E=1
output of bool_logic Z=1
A=1 B=1 C=0 D=0 E=0
output of bool_logic Z=0
A=1 B=1 C=0 D=0 E=1
output of bool_logic Z=0
A=1 B=1 C=0 D=1 E=0
output of bool_logic Z=0
A=1 B=1 C=0 D=1 E=1
output of bool_logic Z=1
A=1 B=1 C=1 D=0 E=0
output of bool_logic Z=0
A=1 B=1 C=1 D=0 E=1
output of bool_logic Z=0
A=1 B=1 C=1 D=1 E=0
output of bool_logic Z=0
A=1 B=1 C=1 D=1 E=1
output of bool_logic Z=1
--
4.
5.
module testbench; //testbench for above modules
reg A,B,C,D,E;
wire Z_bool,Z_gate;
integer i;
bool_logic a1 (.a(A),.b(B),.c(C),.d(D),.e(E),.z(Z_bool)); //instantiation of bool_logic module
gate_logic a2 (.a(A),.b(B),.c(C),.d(D),.e(E),.z(Z_gate)); //instantiation of gate_logic module
initial
begin
for(i=0;i<32;i=i+1)
begin
{A,B,C,D,E}=i; //generating all inputs
#5;
end
end
initial
begin
$monitor ("A=%b B=%b C=%b D=%b E=%b output of bool_logic Z=%b output for gate_logic",A,B,C,D,E,Z_bool,Z_gate);
end
initial
begin
$dumpfile("a1.vcd");
$dumpvars(0,a1);
$dumpfile("a2.vcd");
$dumpvars(0,a2);
end
endmodule
6.output
A=0 B=0 C=0 D=0 E=0
output of bool_logic Z=0
output for gate_logic=0
A=0 B=0 C=0 D=0 E=1
output of bool_logic Z=0
output for gate_logic=0
A=0 B=0 C=0 D=1 E=0
output of bool_logic Z=0
output for gate_logic=0
A=0 B=0 C=0 D=1 E=1
output of bool_logic Z=1
output for gate_logic=1
A=0 B=0 C=1 D=0 E=0
output of bool_logic Z=0
output for gate_logic=0
A=0 B=0 C=1 D=0 E=1
output of bool_logic Z=0
output for gate_logic=0
A=0 B=0 C=1 D=1 E=0
output of bool_logic Z=0
output for gate_logic=0
A=0 B=0 C=1 D=1 E=1
output of bool_logic Z=1
output for gate_logic=1
A=0 B=1 C=0 D=0 E=0
output of bool_logic Z=0
output for gate_logic=0
A=0 B=1 C=0 D=0 E=1
output of bool_logic Z=0
output for gate_logic=0
A=0 B=1 C=0 D=1 E=0
output of bool_logic Z=0
output for gate_logic=0
A=0 B=1 C=0 D=1 E=1
output of bool_logic Z=1
output for gate_logic=1
A=0 B=1 C=1 D=0 E=0
output of bool_logic Z=0
output for gate_logic=0
A=0 B=1 C=1 D=0 E=1
output of bool_logic Z=0
output for gate_logic=0
A=0 B=1 C=1 D=1 E=0
output of bool_logic Z=0
output for gate_logic=0
A=0 B=1 C=1 D=1 E=1
output of bool_logic Z=1
output for gate_logic=1
A=1 B=0 C=0 D=0 E=0
output of bool_logic Z=0
output for gate_logic=0
A=1 B=0 C=0 D=0 E=1
output of bool_logic Z=0
output for gate_logic=0
A=1 B=0 C=0 D=1 E=0
output of bool_logic Z=0
output for gate_logic=0
A=1 B=0 C=0 D=1 E=1
output of bool_logic Z=1
output for gate_logic=1
A=1 B=0 C=1 D=0 E=0
output of bool_logic Z=0
output for gate_logic=0
A=1 B=0 C=1 D=0 E=1
output of bool_logic Z=0
output for gate_logic=0
A=1 B=0 C=1 D=1 E=0
output of bool_logic Z=0
output for gate_logic=0
A=1 B=0 C=1 D=1 E=1
output of bool_logic Z=1
output for gate_logic=1
A=1 B=1 C=0 D=0 E=0
output of bool_logic Z=0
output for gate_logic=0
A=1 B=1 C=0 D=0 E=1
output of bool_logic Z=0
output for gate_logic=0
A=1 B=1 C=0 D=1 E=0
output of bool_logic Z=0
output for gate_logic=0
A=1 B=1 C=0 D=1 E=1
output of bool_logic Z=1
output for gate_logic=1
A=1 B=1 C=1 D=0 E=0
output of bool_logic Z=0
output for gate_logic=0
A=1 B=1 C=1 D=0 E=1
output of bool_logic Z=0
output for gate_logic=0
A=1 B=1 C=1 D=1 E=0
output of bool_logic Z=0
output for gate_logic=0
A=1 B=1 C=1 D=1 E=1
output of bool_logic Z=1
output for gate_logic Z=1
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