Exercises 155 or 31). Describe why the approach you chose is the right approach.
ID: 2085817 • Letter: E
Question
Exercises 155 or 31). Describe why the approach you chose is the right approach. (case, concurrent assignment, structural) 7.7 Multiple-of-3 circuit. Write a VHDL description for a circuit that accepts a four-bit input and outputs true if the input is a multiple of 3 (3, 6, 9, 12, or 15). Describe why the approach you chose (case, concurrent assignment, structural) is the right approach. 7.8 Testbench. Write a VHDL testbench for the multiple-of-3 circuit of Exercise 7.7 7.9 Decimal Fibonacci circuit. Write a VHDL description for a circuit that accepts a iour- input that is guaranteed to be in the range 0-9 and outputs true if the input is a Fibonacc number (0, 1,2,3, 5, or 8). The output is a don't care for input states 10-15. Describe why the approach you chose (case, concurrent assignment, structural) is the right approach. 7.10 Multiple-of-5 circuit. Write a VHDL description for a circuit that outputs true if its fi input is a multiple of 5 7.11 Square circuit. Write a VHDL description for a circuit that outputs true if its eight-bit input is a square number, i.e, 1, 4,9,.... 7.12 Cube cireuit Write a VHDL description for a circuit th at outputs true if its eight-bit input is a cube, i.e., 1, 8,27, 64,.... 7.13 Bit reversal: case. Write a VHDL design entity that takes a five-bit input, input, and outputs a five-bit value that is equal to the input with its bits reversed. For example, 01100 gives output 00110, and input 11110 gives output 01111. You must implement your design entity using a case statement. 7.14 Bit reversal: assign. Write a VHDL design entity that takes a five-bit input, input, and outputs a five-bit value that is equal to the input with its bits reversed. For example, input 01100, gives output 00110 and input 11110 gives output 01111. You must implement your design entity using a single concurrent assignment statement. You will need to use the concatenation operator .15 Next Fibonacci number, I. Write a VHDL design entity that takes in a four-bit input and outputs a five-bit number representing the next Fibonacci number. The mappings of inputs to outputs are as follows: ,0001) = 00010, /(0010)=00011, 0011) 00101, f(0101)= 01000, 1000) 01101, /(1101) = 10101.Explanation / Answer
7.7 ans)
architecture behavioral_process of euler1 is
signal mod3 : integer range 1 to 3;
signal mod4 : integer range 1 to 4;
signal number : integer range 1 to max_count;
signal accumulate3 : std_logic;
signal accumulate5 : std_logic;
signal accumulate_en : std_logic;
signal results_int : unsigned(31 downto 0);
signal results_valid_int : std_logic;
begin -- behavioral
-- purpose: count to 3, provide enables to the accumulator
-- type : sequential
-- inputs : clk, reset, enable
-- outputs: mod3
modulus3 : process (clk, reset)
begin -- process mod3
if reset = '1' then -- asynchronous reset (active high)
mod3 <= 1;
elsif rising_edge(clk) then -- rising clock edge
if enable = '1' then
if mod3 = 3 then
mod3 <= 1;
else
mod3 <= mod3 + 1;
end if; -- mod3 if
end if; -- enable
end if; -- clk
end process modulus3;
accumulate3 <= '1' when mod3 = 3 else '0';
-- purpose: count to 4, provide enables to the accumulator
-- type : sequential
-- inputs : clk, reset, enable
-- outputs: mod3
modulus5 : process (clk, reset)
begin -- process mod3
if reset = '1' then -- asynchronous reset (active high)
mod5 <= 1;
elsif rising_edge(clk) then -- rising clock edge
if enable = '1' then
if mod5 = 5 then
mod5 <= 1;
else
mod5 <= mod5 + 1;
end if; -- mod5 if
end if; -- enable
end if; -- clk
end process modulus5;
accumulate5 <= '1' when mod5 = 5 else '0';
accumulate_en <= accumulate5 or accumulate3;
-- purpose: count from 1 to max_count
-- type : sequential
-- inputs : clk, reset, enable
-- outputs: number
number_generator : process (clk, reset)
begin -- process number_generator
if reset = '1' then -- asynchronous reset (active high)
number <= 1;
results_valid_int <= '0';
elsif rising_edge(clk) then -- rising clock edge
if enable = '1' then
if number /= max_count then
number <= number + 1;
else
results_valid_int <= '1';
end if;
else
results_valid_int <= '0';
end if;
end if;
end process number_generator;
-- purpose: accumulate the numbers divisible by 3 and 5
-- type : sequential
-- inputs : clk, reset, number, accumulate_en
-- outputs: results
accumulator : process (clk, reset) is
begin -- process accumulator
if reset = '1' then -- asynchronous reset (active high)
results_int <= (others => '0');
elsif rising_edge(clk) then -- rising clock edge
if accumulate_en = '1' and results_valid_int = '0' then
results_int <= results_int + number;
end if;
end if;
end process accumulator;
7.9 ans)
architecture behavioral of euler2 is
signal even : std_logic;
signal results_int : unsigned(31 downto 0);
signal results_valid_int : std_logic;
signal fib_r1 : unsigned(31 downto 0);
signal fib_r2 : unsigned (31 downto 0);
signal sum : unsigned (31 downto 0);
begin -- behavioral
-- fibonacci registers and accumulator for fibonacci evens
fib_reg : process (clk, reset) is
begin -- process R1
if reset = '1' then
fib_r1 <= x"00000001";
fib_r2 <= (others => '0');
results_int <= (others => '0');
elsif rising_edge(clk) then
if enable = '1' then
fib_r1 <= sum;
fib_r2 <= fib_r1;
if even = '1' and results_valid_int = '0' then
results_int <= results_int + sum;
end if;
end if;
end if;
end process fib_reg;
sum <= fib_r1 + fib_r2;
even <= '1' when sum(0) = '0' else '0';
results_valid_int <= '1' when sum >= max_count else '0';
results_valid <= results_valid_int;
results <= results_int;
end behavioral;
7.11)
library ieee;
use numeric_std.all;
entity square is
port (
x : in unsigned( 7 downto 0);
x_squared : out unsigned(15 downto 0)
)
end entity square;
architecture rtl of square is
begin
x_squared <= x*x;
end architecture rtl;
7.12_
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_unsigned.ALL;
entity squart is port(
clock : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(3 downto 0)); end cubert;
architecture behaviour of squart is
signal part_done : std_logic := '0';
signal part_count : integer := 3;
signal result : std_logic_vector(4 downto 0) := "00000";
signal partialq : std_logic_vector(5 downto 0) := "000000";
begin
part_done_1: process(clock, data_in, part_done)
begin
if(clock'event and clock='1')then
if(part_done='0')then
if(part_count>=0)then
partialq(1 downto 0) <= data_in((part_count*2)+ 1 downto part_count*2);
part_done <= '1'; else
data_out <= result(3 downto 0);
end if;
part_count <= part_count - 1;
elsif(part_done='1')then
if((result(3 downto 0) & "01") <= partialq)then
result <= result(3 downto 0) & '1';
partialq(5 downto 2) <= partialq(3 downto 0) - (result(1 downto 0)&"01");
else
result <= result(3 downto 0) & '0';
partialq(5 downto 2) <= partialq(3 downto 0);
end if;
part_done <= '0';
end if;
end if;
end process;
end behaviour;
7.13)
library ieee;
use ieee.std_logic_1164.all;
entity reverser is
port(
a: in std_logic_vector(7 downto 0);
y: out std_logic_vector(7 downto 0);
rev: in std_logic
);
end reverser;
architecture rtl of reverser is
signal b: std_logic_vector (7 downto 0);
begin
b(7) <= a(0);
b(6) <= a(1);
b(5) <= a(2);
b(4) <= a(3);
b(3) <= a(4);
b(2) <= a(5);
b(1) <= a(6);
b(0) <= a(7);
y <= b when rev = '1' else a;
end rtl;
results <= results_int;
results_valid <= results_valid_int;
end behavioral_process;
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