The TTL Data Book lists the following switching times for gates from the ICs use

Question

The TTL Data Book lists the following switching times for gates from the ICs used in Lab 3:

74LS00:             Max (LO to HIGH): 10 ns      Max (HIGH to LO) 10 ns      

74LS02:             Max (LO to HIGH): 13 ns      Max (HIGH to LO) 10 ns

74LS04:             Max (LO to HIGH): 22 ns      Max (HIGH to LO) 15 ns

74LS08:             Max (LO to HIGH): 13 ns      Max (HIGH to LO) 11 ns

74LS10:             Max (LO to HIGH): 10 ns      Max (HIGH to LO) 10 ns

74LS32:             Max (LO to HIGH): 11 ns      Max (HIGH to LO) 11 ns

In light of these values, calculate the maximum total gate delay for your circuits from parts C, E, and F of the preliminary design. What conclusions can you draw with regard to: (a) using NAND gates vs. using AND and OR gates? (b) using two-level logic vs. implementing circuits whose critical paths are longer than two?

Here are the circuits I made, but I'm not sure how to calclate the maximum total gate delay. I understand which series of gates have the longest delay (typically an input that goes through the most gates before it approaches the output), but with the given table, I'm not sure how to calculate that delay from "LO to HIGH" and "HIGH to LO" as there should only be one switch time.

U4:C U1:A U3:A U1:B 741S09 TALS32 U1:C 74LS08 4LS08 U4:A U1:D 4LS04 U2:A ALS08 4LS08 U3:B 74LS32 U2:B U4:B 74LS08 74L5D4 U2:C U2:D 4LS08 4LS08 1 (C) Figure 1: Majority Circuit (unsimplified) Represented through a Complex Series of Hex Inverters and AND/OR Gates $4.53 74LS32

Explanation / Answer

HERE YOU USED 74LS FAMILY

74LS00----QUAD 2I/P NAND GATE

74LS02---QUAD 2I/P NOR GATE

74LS04--HEX INVERTER

74LS08---QUAD 2I/P AND GATE

74LS10---TRIPLE 3I/P NAND

74LS32---QUAD 2I/P OR GATE

74LS (Low-power Schottky) family uses TTL (Transistor-Transistor Logic) circuitry which is fast but requires more power than later families. The 74 series is often still called the 'TTL series' even though the latest ICs do not use TTL

74LSxx: Low Power Schottky TTL – Same as 74Sxx types but with increased internal resistances to improve power consumption. Supply voltage range: 4.75 to 5.25v

In electronics, digital circuits and digital electronics, the propagation delay, or gate delay, is the length of time which starts when the input to a logic gate becomes stable and valid to change, to the time that the output of that logic gate is stable and valid to change

DEPEND ON THE DESIGN PARAMETERS WE CAN CALCULATE tp=1/2(tphl+tplh)

depens on the propagation delay value we have to calculate the trace length and we need backplane connector value

with these value we can calculate the required total gate delay

for example : if propagation delay =0.8inches =2.032cmapprox=0.137ns

trace length=0.170ns here we can calculate it as trace propagation delay=1 inch=2.54cm

backplane connector=0.135ns

total gate delay= (0.137nS x 4 slots) + (0.17nS x 2 traces) + (0.135nS x 2 connectors)

1.158ns

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