We have seen how all RISC-style instructions can be executed using the steps in

Question

We have seen how all RISC-style instructions can be executed using the steps in Figure 5.4 on the multi-stage hardware of Figure 5.8. Autoincrement and Autodecrement addressing modes are not included in RISC-style instruction sets. Explain why the instruction Load R3, (R5)+ cannot be executed on the hardware in Figure 5.8.

Step Action 1 Fetch an instruction and increment the program counter. 2 Decode the instruction and read registers from the register file. 3 Perform an ALU operation. 4 Read or write memory data if the instruction involves a memory operand. Write the result into the destination register, if needed. Figure 5.4 A five-slep sequence of actions to fetch and execute an instruction.

Explanation / Answer

As explained in the table of figure 5.4, every instruction has five stages in which it is executed. Initially it fetches the instruction and increments the program counter, then it decides the instruction and reads the contents from the register which are required for the execution of the instruction. then it performs a ALU operation of required. Then if there is any memory dependency in the instruction then it either fetches or writes the contents in the memory.Then at last in the fifth stage it writes the contents back in the register if required. So for the given instruction LOAD R3,(R5)+ it means that we have to get read the memory contents present in the address given in R5 incremented by one in other words known as auto increment and then put those contents in R3. So as you can see, first we will fetch the instruction decode it as we do for all the instructions then RB has the contents of R5 which has the address of the memory location. But we need to read the contents present in next address given by R5 but using the given hardware or architecture there is no mechanism by which we can increment the address by one and read the memory contents in the same instruction's execution. So we can't get the correct contents to be stored in R3 as we can only get contents present in R5 not R5+ that is the next location. so using the given hardware we can't execute the given instruction.

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