COMPLETE VERILOG SOURCE CODE FOR TEMPLATE MODULES Part 1. Develop a module BCD2L

Question

COMPLETE VERILOG SOURCE CODE FOR TEMPLATE MODULES

Part 1. Develop a module BCD2LEDS to display a 4-bit binary-coded-decimal (BCD) on 7-segment display. Follow the Verilog template below for the sub-module module BCD2LEDS (bcd, leds): input [3:0] bcd//0000 to 1001 assumed output reg [6:0] leds; always @() case (bcd) 2 4'b0000: leds-7'b 100000;// low active LEDs endcase Test the module in Quartus II and on the DE-2 board. Use an instance of the submodule inside a top module. Use SW3-SWO as the BCD number input. Use HEX0 as the 7-segment display. module lab2part1(SW,HEXO); input [3:0] SW; output [6:0] HEXO; // why not reg here? BCD2LEDS U0(SW,HEXO)://module instantiation endmodule

Explanation / Answer

module BCD2LEDS (bcd,leds);

input [3:0] bcd;

output reg [6:0] leds;

always @(*)

begin

case (bcd)

4'b0000:leds=7'b1000000;

4'b0001:leds=7'b1111001;

4'b0010:leds=7'b0100100;

4'b0011:leds=7'b0110000;

4'b0100:leds=7'b0011001;

4'b0101:leds=7'b0010010;

4'b0110:leds=7'b0000010;

4'b0111:leds=7'b1111000;

4'b1000:leds=7'b0000000;

4'b1001:leds=7'b0011000;

default:leds=7'b0001001;

endcase

end

endmodule

module lab2part1 (SW,HEX0);

input [3:0] SW;

output [6:0] HEX0; // reg can be assigned values only in always block continious assignment to reg variable is not possible

BCD2LEDS U0 (SW,HEX0);

endmodule

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