1. Fig. 1 shows the architecture of a RISC computer and its instruction format.

Question

1. Fig. 1 shows the architecture of a RISC computer and its instruction format. The instrcutions are: Load (L), Store (S), Branch (B), Jump (J), Register-to-Register (R2R), and Reserved (X). Bit 25 is the literal bit. Some of typical operations are:
LDR D,(S1,S2) [D] [M([S1] + [S2])] Register indirect with double indexing
LDR D,(S1,#L) [D] [M([S1] + L)] Register indirect with literal offset
STR (S1,#L),S2 [M([S1] + L)] [S2] Register indirect with literal offset
ADD D,S1,S2 [D] [S1] + [S2] Register to register
ADD D,S1,#L [D] [S1] + L Register to register with literal operand
BEQ L [PC] [PC] + 4 + L This is a relative conditional branch
JMP (S1,#L)

Assume r1=2B0016, r2=C16, answer the following questions:
(1) Show 32-bit number of each of the following instructions. (for unused bits, marked by “x”)
LDR r0, (r1,r2)
LDR r0,(r2, #33)
STR (r1,#65),r2
ADD r0,r1,r2
ADD r0,r2,#49
BEQ 50
JMP (r1,#100)

Register file addeoss S S2addsss S2data Data Memory S1 PC ALU 0 Instruction Memory ala in Select ALU Select second operand as S2 or literal. output or memory data 4 MPLX Lett shift x2 Select PC as next in sequence computed jump, or literal. Registers S2 Literal S1 | S | B | J R2R| X | # | Parameters |Source 1|Source 2|Destination Literal 31 30 29 28 27 26 25 24 21 20 18 17 15 14 12 11 Fig.1 (a) Architecture of a hypothetical RISC computer; (b) Instruction format

Explanation / Answer

LDR r0, [r1,r2]

this instruction loads the memory content pointed by (r1+r2 ) i.e 2B0C2C in r0 register.

32 bit hex value is E7910002

LDR r0,(r2, #33)

this instruction loads the memory content pointed by (r2+33 ) i.e C49 in r0 register.

32 bit hex value is E5920021

ADD r0,r1,r2

ADD r1 and r2 and store in r0.

32 bit hex value is E0810002

ADD r0,r2,#49

32 bit hex value is E2820031

BEQ 50

32 bit hex value is 0A00000A

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