I did the verliog and I don\'t how to do VHDL assign g[0] = (X[0] & ( Y[0] ^ As_

Question

I did the verliog and I don't how to do VHDL

assign g[0] = (X[0] & ( Y[0] ^ As_Sel));
assign g[1] = (X[1] & ( Y[1] ^ As_Sel));
assign g[2] = (X[2] & ( Y[2] ^ As_Sel));
assign g[3] = (X[3] & ( Y[3] ^ As_Sel));

assign P[0] = X[0] | ( Y[0] ^ As_Sel);
assign P[1] = X[1] | ( Y[1] ^ As_Sel);
assign P[2] = X[2] | ( Y[2] ^ As_Sel);
assign P[3] = X[3] | ( Y[3] ^ As_Sel);

assign C[1] = g[0] | (P[0] & As_Sel);
assign C[2] = g[1] | P[1] & C[1];
assign C[3] = g[2] | P[2] & g[1] | P[1] & g[0] | P[0] & As_Sel;
assign C[4] = g[3] | P[3] & C[3];

assign S[0] = X[0] ^ ( Y[0] ^ As_Sel) ^ As_Sel;
assign S[1] = X[1] ^ ( Y[1] ^ As_Sel) ^ (C[1]);
assign S[2] = X[2] ^ ( Y[2] ^ As_Sel) ^ (C[2]);
assign S[3] = X[3] ^ ( Y[3] ^ As_Sel) ^ (C[3]);

these are equations that you have to use them

1) 2) From mycourses download on your desktop this pdf file This lab consists of two parts: A VHDL functional implementation and simulation of a 4-bit CLA. A Verilog functional implementation and simulation of a 4-bit CLA a. b. 3) Objective: The objective of this lab exercise is to design and verify using a testbench, i.e through simulation, a CLA The structure and functionality of the CLA was covered in part 2 Paper and pencil preparatory design 4) 5) a. b. c. Derive all propagate and generate functions Express all carries as a function of co, propagate, and generate functions Express all sum bits as a function of the above 6) Use concurrent assignments statements in the body of your code. You don't need to use a procedural statement. 7) You need to test the same combinations as in lab 4. Thus, you can adapt and re-use those testbenches Inputs Expected Good Outputs Cin Co AS_Sel 0 Cout-C 0101 1010 1110 1010 0100 0101 0 0 1010 0101 1010 0101 1010

Explanation / Answer

-- Design file of a 4bit Carry Look Ahead ADDER
library ieee;
use ieee.std_logic_1164.all;

entity cla_adder is
port (
   X      : in std_logic_vector (3 downto 0);
   Y      : in std_logic_vector (3 downto 0);
   AS_Sel : in std_logic ;
   S      : out std_logic_vector (3 downto 0);
   Cout   : out std_logic
);
end cla_adder;

architecture rtl of cla_adder is

signal g : std_logic_vector (3 downto 0) ;
signal P : std_logic_vector (3 downto 0) ;
signal C : std_logic_vector (4 downto 0) ;

begin
   g(0) <= (X(0) and (Y(0) xor AS_Sel));  
   g(1) <= (X(1) and (Y(1) xor AS_Sel));  
   g(2) <= (X(2) and (Y(2) xor AS_Sel));  
   g(3) <= (X(3) and (Y(3) xor AS_Sel));  

   P(0) <= (X(0) or (Y(0) xor AS_Sel));
   P(1) <= (X(1) or (Y(1) xor AS_Sel));
   P(2) <= (X(2) or (Y(2) xor AS_Sel));
   P(3) <= (X(3) or (Y(3) xor AS_Sel));

   C(0) <= AS_Sel;
   C(1) <= (g(0) or (P(0) and AS_Sel));
   C(2) <= (g(1) or (P(1) and C(1)));
   C(3) <= (g(2) or (P(2) and C(2)));
   C(4) <= (g(3) or (P(3) and C(3)));

   S(0) <= (X(0) xor (Y(0) xor AS_Sel) xor AS_Sel);
   S(1) <= (X(1) xor (Y(1) xor AS_Sel) xor C(1)) ;
   S(2) <= (X(2) xor (Y(2) xor AS_Sel) xor C(2)) ;
   S(3) <= (X(3) xor (Y(3) xor AS_Sel) xor C(3)) ;
   Cout <= C(4);

end rtl;

-- Testbench file of a 4bit Carry Look Ahead ADDER
library ieee;
use ieee.std_logic_1164.all;

entity cla_adder_tb is
end cla_adder_tb;

architecture behav of cla_adder_tb is
constant c_WIDTH : integer := 4;

signal r_ADD_1 : std_logic_vector(c_WIDTH-1 downto 0);
signal r_ADD_2 : std_logic_vector(c_WIDTH-1 downto 0);
signal r_AS_SEL : std_logic ;
signal w_RESULT : std_logic_vector(c_WIDTH-1 downto 0);
signal w_COUT   : std_logic ;

component cla_adder
    generic ( g_WIDTH : natural);
    port (
      X      : in std_logic_vector (3 downto 0);
      Y      : in std_logic_vector (3 downto 0);
      AS_Sel : in std_logic ;
      S      : out std_logic_vector (3 downto 0);
      Cout   : out std_logic
    );
end component;

begin
   UUT : cla_adder
        generic map (g_WIDTH => c_WIDTH)
         port map (
           X      => r_ADD_1,
           Y      => r_ADD_2,
           AS_Sel => r_AS_Sel,
           S      => w_RESULT,
           Cout   => w_COUT
        );

   process
   begin
     r_AS_Sel <= '0';
     r_ADD_1 <= "1100";
     r_ADD_2 <= "1000";
     wait for 10 ns;

     r_AS_Sel <= '0';
     r_ADD_1 <= "1111";
     r_ADD_2 <= "0110";
     wait for 10 ns;

     r_AS_Sel <= '0';
     r_ADD_1 <= "0101";
     r_ADD_2 <= "0101";
     wait for 10 ns;

     r_AS_Sel <= '0';
     r_ADD_1 <= "0100";
     r_ADD_2 <= "1000";
     wait for 10 ns;

     r_AS_Sel <= '0';
     r_ADD_1 <= "1110";
     r_ADD_2 <= "0001";
     wait for 10 ns;

     r_AS_Sel <= '0';
     r_ADD_1 <= "0011";
     r_ADD_2 <= "1001";
     wait for 10 ns;

     r_AS_Sel <= '1';
     r_ADD_1 <= "1100";
     r_ADD_2 <= "1000";
     wait for 10 ns;

     r_AS_Sel <= '1';
     r_ADD_1 <= "1111";
     r_ADD_2 <= "0110";
     wait for 10 ns;

     r_AS_Sel <= '1';
     r_ADD_1 <= "0101";
     r_ADD_2 <= "0101";
     wait for 10 ns;

     r_AS_Sel <= '1';
     r_ADD_1 <= "0100";
     r_ADD_2 <= "1000";
     wait for 10 ns;

     r_AS_Sel <= '1';
     r_ADD_1 <= "1110";
     r_ADD_2 <= "0001";
     wait for 10 ns;

     r_AS_Sel <= '1';
     r_ADD_1 <= "0011";
     r_ADD_2 <= "1001";
     wait for 10 ns;
   end process;

end behav;

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