State Machine Create a 2-input sequence detector as a verilog module. Design the

Question

State Machine

Create a 2-input sequence detector as a verilog module. Design the machine to use a push button 2 to work as the clock, push button 3 to work as a reset and the dip switches 1 and 0 to work as inputs which are captured at each push of button 2 Detect a (1,0) (1,0) (1,1) sequence or a (1,1) (1,1) (1,1) sequence. Bear in mind that the button used as the clock is really a synchronizing event and not an actual clock as used with a posedge in Verilog. Create a one cycle pulse from each rising edge and use this as a data enable to advance the state machine

Explanation / Answer

module sm1(PB2,PB3,DIP1,DIP2,Y); input PB2; //clk input PB3; //rst input DIP1; //dip switch 1 input DIP2; //dip switch 2 output reg Y; //output parameter idle=2'b00, pat_11=2'b01, pat_21=2'b10, pat_12=2'b11; reg [1:0] pstate,nstate; always @(posedge PB2) begin if(PB3) pstate

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