8. Suppose r0 0xFFFFFFFF, r1 = 0x00000001, r2 = 0x00000000 Initially N, Z, C, V

Question

8. Suppose r0 0xFFFFFFFF, r1 = 0x00000001, r2 = 0x00000000 Initially N, Z, C, V flags are zero. Find the value of the N, Z, C, V flags of the following instructions. (Assume each instruction runs individually, i.e. these instructions are not part of a program.) () ADD r3, r0, r2 (2) SUBS r3, r0, r0 8) ADDS r3, r0, r2 9. Suppose we have a hypothetical processor, of which each register has only five bits. r0 = 0b11101 and rl = 0b10110. What are the N, Z, C, V flags of the following instructions? Assume initially N = 0, Z = 0, C = 1, V = 0, and these instructions are executed independently (i.e. they are NOT part of a program) )ADDS r3, r0, rl a) SUBS r3, r0, rl

Explanation / Answer

Answer:-

If the current instruction is a data processing instruction, and the flags are to be updated by it, the instruction must be postfixed by an S. The exceptions to this are
CMP, CMN, TST and TEQ, which always update the flags (since this is their only effect).

Examples:-

ADD r0, r1, r2 ; ro = r1 + r2, don’t update flags
ADDS r0, r1, r2 ; r0 = r1 + r2 and UPDATE flags

N:- sets to 1 when result is negative in 32-bit
Z:- sets to 1 when result is zero in 32-bit
C:- sets to 1 when result is more than 32-bit number(signed and unsigned both)
V:- sets to 1 when result is 32-bit number(only for 2's complement signed number)

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r0 = 0xFFFFFFFF, r1 = 0x00000001, r2 = 0x00000000 then

i) ADD r3, r0, r2 :- No flag sets since 'S' is not postfixed to ADD.

ii) SUBS r3, r0, r0 :- r3 = r0 – r0 = 0x00000000, Flags set as,
N = 0, since result is zero and it's a positive number.
Z = 1, since result is zero
C = 0, result is not generating any carry
V = 0, value zero can be accomodated in 32-bit system

iii) ADDS r3, r0, r2 :- r3 = r0 + r2 = 0xFFFFFFFF, Flags set as,
N = 1, since 0xFFFFFFFF is equal to -1 in 2's complement form
Z = 0, result is not zero
C = 0, No carry is comming
V = 0, result 0xFFFFFFFF can be stored as 32-bit value

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