Modify module BCDADD1 from half adder to full adder to add two-digit BCDs: modul

Question

Modify module BCDADD1 from half adder to full adder to add two-digit BCDs:  

module lab2part4(SW, HEX0,HEX1,HEX2, HEX3);
input [7:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3;
wire S1; // internal signal for the carry-out bit (tens)
wire [3:0] S0;// internal signal for the BCD sum (ones)
BCD2LEDS U0(SW[3:0],HEX0);//HEX0
BCD2LEDS U1(SW[7:4],HEX1);//HEX1
BCD2LEDS U2(S0,HEX2);//HEX2
BCD2LEDS U3({3'B000,S1},HEX3);//HEX3
BCDADD1 U4(SW[3:0],SW[7:4],S0,S1);
endmodule

module BCDADD1(A0,B0,S0,S1);
input [3:0] A0, B0; //4 bit inputs
output reg [3:0] S0; // 4bit sum why not wire typ?
output reg S1;// 1 bit carry-out
always @(*)
begin
{S1,S0}=A0+B0; // 4-bit add 4-bit to produce 4 bit result and 1 bit carry out
if (A0+B0>9) // otherwise, no correction, S1=0, S0=A0+B0
begin
S0=A0+B0-10;// or S0=A0+B0+6// to have ‘ones’ in S0 as 3 in 13
S1=1;// carry-out
end
end
endmodule

module BCD2LEDS (bcd,leds);
input [3:0] bcd;
output reg [6:0] leds;
always @(*)
case (bcd)
4'b0000:leds=7'b1000000;
4'b0001:leds=7'b1111001;
4'b0010:leds=7'b0100100;
4'b0011:leds=7'b0110000;
4'b0100:leds=7'b0011001;
4'b0101:leds=7'b0010010;
4'b0110:leds=7'b0000010;
4'b0111:leds=7'b1111000;
4'b1000:leds=7'b0000000;
4'b1001:leds=7'b0010000;
default:leds=7'b1111111;
endcase
endmodule

Part 4. Design a module BCDAdd2 to add two-digit BCDs S2 S1 SO A1A0+B1B0 (two digit adds into another two digits to generate 3-digit sum, where S2 is the carry out digit). top module module lab2part4(SW, HEXO, HEX1, HEX2, HEX3, HEX4, HEX5);// how many switches? sub-module files BCDADD1FA.v// modify BCDADD1 from a half-adder to a full-adder by adding a carry-in bit module BCDADD1FA(AO,BO,Cin, SO, Cout); // AO, BO, S0 4bits, Cin, Cout single bits BCDLEDS.v BCDADD1.v// optional

Explanation / Answer

module BCDADD1(A1,A0,B1,B0,S0,S1,S2);
input [3:0] A1, A0, B1, B0; //4 bit inputs
output reg [3:0] S0,S1; // 4bit sum why not wire typ?
output reg S2;// 1 bit carry-out

wire S1carry;
always @(*)
begin

//LSB addition

{S1carry,S0}=A0+B0; // 4-bit add 4-bit to produce 4 bit result and 1 bit carry out
if (A0+B0>9) // otherwise, no correction, S1=0, S0=A0+B0
begin
S0=A0+B0-10;// or S0=A0+B0+6// to have ‘ones’ in S0 as 3 in 13
S1carry=1;// carry-out

//LSB+1 addition

{S2,S1}=A1+B1+S1carry; // 4-bit add 4-bit to produce 4 bit result and 1 bit carry out
if (A1+B1+S1carry>9) // otherwise, no correction, S1=0, S0=A0+B0
begin
S1=A1+B1+S1carry-10;// or S0=A0+B0+6// to have ‘ones’ in S0 as 3 in 13

S2=1;// carry-out

end

end
endmodule

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