An internal adder is to be replaced by the clocked serial adder shown below. Exa

Question

An internal adder is to be replaced by the clocked serial adder shown below. Examine the given diagram with an unsigned 8-bit addition example and determine the following:

a. How many cycles after the load operation will the final Sum and Cout be available?

b. Is it possible to for a carry-in C0 = 0? or C1 = 1?

c. Is it possible to incorporate a subtract function? How?

Shift register Sum bit D Q Full Shift register AddrCary-ou Shift register Sum A+ B Clock Clock D Q Cout Parallel input Clock Shift register Reset Clock

Explanation / Answer

(a) In 8 clock cycles, shift registers A & B will be able to provide inputs to Full adder block sequentially.. Hence after 8 clock cycles final sum and cout will be available.

(b) For the first set of bits (LSB) coming from shift registers A & B should be added by full adder with C0 = 0. Hence a reset (active Low) signal at D flip flop will do the required for the first bit addition with carry =0. For subsequent bits addition D Flip Flop will register previous carries.

(c) For substraction, either of the operands A/B needs to be 1's complemented or 2'complemented. Using extra NOT gates it can be achieved along with the full adder

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