Need a testbench for each of the Verilog Modules listed below //ALU module alu(
ID: 2250103 • Letter: N
Question
Need a testbench for each of the Verilog Modules listed below
//ALU
module alu(
input wire [31:0] op1,
input wire [31:0] op2,
input wire [3:0] ctrl,
output reg [31:0] result,
output zero
);
always @(op1, op2, ctrl)
case (ctrl)
3'b000: result = op1 & op2;
3'b001: result = op1 | op2;
3'b010: result = op1 + op2;
3'b110: result = op1 - op2;
3'b111: result = op1 < op2;
3'b101: result = op1 | ~op2;
endcase
assign zero = result == 0;
endmodule
//2-to-1 Mux
module twotoonemux(
input wire [31:0] input1,
input wire [31:0] input2,
input wire sel,
output wire [31:0] outputval
);
always @(in0, in1, sel)
case (sel)
1'b0: out <= in0;
1'b1: out <= in1;
endcase
endmodule
//Register File
module registerfile(
input wire [4:0] readReg1,
input wire [4:0] readReg2,
input wire [4:0] writeReg,
input wire [31:0] writeData,
input wire regWrite,
output reg [31:0] readData1,
output reg [31:0] readData2
);
//Sign Extend
module signextend(
input wire [15:0] inputVal,
output wire [31:0] outputVal
);
assign outputVal = {{16{inputVal[15]}}, inputVal};
endmodule
Explanation / Answer
module t_alu;
wire op1, op2, result;
reg [3:0] ctrl;
alu A(op1, op2, ctrl, result);
Initial
begin
ctrl = 3'b000;
repeat (7) #10 ctrl = ctrl + 3'b000;
end
endmodule
module t_twotoonemux;
wire input1, input2, outputval;
reg sel;
twotoonemux B(input1, input2, sel, outputval);
Initial
begin
sel = 1'b0;
repeat (2) #10 sel = sel + 1'b1;
end
endmodule
module t_registerfile;
wire readReg1;
wire readReg2;
wire writeReg;
wire writeDat;
wire regWrite;
wire readData1;
wire readData2;
registerfile C(readReg1, readReg2, writeReg, writeDat, regWrite, readData1, readData2);
endmodule
module t_signextend;
wire inputVal;
wire outputVal;
signextend D(inputval, outputval);
endmodule
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