Using ISE WebPACK Design Software Part 1: Build a 4 to 1 Multiplexer in schemati
ID: 2250117 • Letter: U
Question
Using ISE WebPACK Design Software
Part 1: Build a 4 to 1 Multiplexer in schematic and test it in the simulation EN S1 SO MuxOUT 0 Part 2: Build an 8 to 1 multiplexer from two 4 to 1 multiplexers in schematic and: » Test it in the simulation * Test it in the Nexys 4 board (bonus) S2 S1 0 0 SO MuxOUT 0 0 0 0 0 0 0 Submit the following for this assignment: . Submit a word file as a report that includes: o The two tables of Part 1 and 2 o Schematics for Part 1 and 2. o Screenshot for the simulation of Part 1. o Screenshot for the simulation of Part 2. Demonstration for Part 2 (bonus) .Explanation / Answer
Verilog Code for 4 x 1 Mux:
module mux4bit( s, a, o )
input[1:0] s;
input[3:0] a;
output o;
wire o;
wire[1:0] s;
wire[3:0] a;
assign o = a[s];
endmodule
Testbench code for 4 x 1 Mux:
module mux4t_b;
reg [1:0] s;
reg [3:0] a;
wire o;
mux4bit uut (.s(s),.a(a), .o(o));
initial begin
#10 a=4’b1010;
#10 s=2’b00;
#10 s=2’b01;
#10 s=2’b10;
#10 s=2’b11;
#10 $stop;
end
endmodule
Verilog Code for 8 x 1 Mux:
module mux2bit( s, a, o );
input s;
input[1:0] a;
output o;
wire o;
wire s;
wire[1:0] a;
assign o = a[s];
endmodule
module mux4bit( s, a, o );
input[1:0] s;
input[3:0] a;
output o;
wire o;
wire[1:0] s;
wire[3:0] a;
assign o = a[s];
endmodule
module mux8bit(a,sel,out);
input [7:0] a;
input [2:0] sel;
output out;
wire mux[2:0];
mux4to1 m1 (a[7:4],sel[1:0],mux_1),
m2 (a[3:0],sel[1:0],mux_2);
mux2to1 m3 (mux_1,mux_2,sel[2],out);
endmodule
Testbench code for 8 x 1 Mux:
module mux8bit_b;
reg [2:0] s;
reg [7:0] a;
wire o;
mux8bit uut (.s(s),.a(a), .o(o));
initial begin
#10 a=8’b10101010;
#10 s=3’b000;
#10 s=3’b001;
#10 s=3’b010;
#10 s=3’b011;
#10 s=3’b100;
#10 s=3’b101;
#10 s=3’b110;
#10 s=3’b111;
#10 $stop;
end
endmodule
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