Sment 1u7 Traffic Light Controller A busy road intersection has two roads, a maj
ID: 2250210 • Letter: S
Question
Sment 1u7 Traffic Light Controller A busy road intersection has two roads, a major road and a minor roud. A traffic light controller is to be designed to properly operate the traffic lights. The normal or idle state of the controller is the major road green light on and the minor road red light or. The minor road has vehicle sensors that send a 1 to the controller when a vehicle is detected. When the sensor is 1, the major road lights sequence from green to yellow and then to red, while the minor road lights go from red to yellow to green in accordance with the timing specifications shown in Table 1 Major Road Minor Road Delay (sec) Idle S0 Green Green Yellow Red Red Red Red Red Red Green YelloW Red Infinite 10 S2 S3 S4 S5 Red Design and implement the controller in VHDExplanation / Answer
library ieee;
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity controller is
port (clk : in std_logic; ---assuming clock is of 1 sec period
rst : in std_logic;
sensor_minor : in std_logic;
red_major : out std_logic;
yellow_major : out std_logic;
green_major : out std_logic;
red_minor : out std_logic;
yellow_minor : out std_logic;
green_minor : out std_logic
);
end controller;
architecture arch of controller is
signal delay_counter : std_logic_vector(3 downto 0);
signal delay10s, delay5s, delay2s : std_logic;
type state is (idle, s0, s1, s2, s3, s4, s5);
signal present_state, next_state : state;
begin
process (clk, rst)
begin
if (rst = ‘1’) then --asynchronous reset
present_state <= idle;
elsif rising_edge (clk) then
present_state <= next_state;
end if;
end process;
process (present_state, sensor_minor, delay_counter)
begin
case (present_state) is
when idle =>
red_major <= ‘0’;
yellow_major <= ‘0’;
green_major <= ‘1’;
red_minor <= ‘1’;
yellow_minor <= ‘0’;
green_minor <= ‘0’;
if (sensor_minor = ‘1’) then
next_state <= s0;
else
next_state <= idle;
end if;
when s0 =>
red_major <= ‘0’;
yellow_major <= ‘0’;
green_major <= ‘1’;
red_minor <= ‘1’;
yellow_minor <= ‘0’;
green_minor <= ‘0’;
if (delay10s = ‘1’) then
next_state <= s1;
else
next_state <= s0;
end if;
when s1 =>
red_major <= ‘0’;
yellow_major <= ‘1’;
green_major <= ‘0’;
red_minor <= ‘1’;
yellow_minor <= ‘0’;
green_minor <= ‘0’;
if (delay2s = ‘1’) then
next_state <= s2;
else
next_state <= s1;
end if;
when s2 =>
red_major <= ‘1’;
yellow_major <= ‘0’;
green_major <= ‘0’;
red_minor <= ‘1’;
yellow_minor <= ‘0’;
green_minor <= ‘0’;
if (delay2s = ‘1’) then
next_state <= s3;
else
next_state <= s2;
end if;
when s3 =>
red_major <= ‘1’;
yellow_major <= ‘0’;
green_major <= ‘0’;
red_minor <= ‘0’;
yellow_minor <= ‘0’;
green_minor <= ‘1’;
if (delay5s = ‘1’) then
next_state <= s4;
else
next_state <= s3;
end if;
when s4 =>
red_major <= ‘1’;
yellow_major <= ‘0’;
green_major <= ‘0’;
red_minor <= ‘0’;
yellow_minor <= ‘1’;
green_minor <= ‘0’;
if (delay2s = ‘1’) then
next_state <= s5;
else
next_state <= s4;
end if;
when s5 =>
red_major <= ‘1’;
yellow_major <= ‘0’;
green_major <= ‘0’;
red_minor <= ‘1’;
yellow_minor <= ‘0’;
green_minor <= ‘0’;
if (delay2s = ‘1’) then
next_state <= idle;
else
next_state <= s5;
end if;
when others => next_state <= idle;
end case;
end process;
-- Generate delays of 10s/5s/2s
process (clk)
begin
if rising edge (clk) then
if (present_state = s0) then
if (delay_counter = “1010”) then
delay10s <= ‘1’;
delay_counter <= “0000”;
else
delay_counter <= delay_counter + 1;
delay10s <= ‘0’;
end if;
end if;
if (present_state = s1 or present_state = s2 or present_state = s4 or present_state = s5) then
if (delay_counter = “0010”) then
delay2s <= ‘1’;
delay_counter <= “0000”;
else
delay_counter <= delay_counter + 1;
delay2s <= ‘0’;
end if;
end if;
if (present_state = s3) then
if (delay_counter = “0101”) then
delay5s <= ‘1’;
delay_counter <= “0000”;
else
delay_counter <= delay_counter + 1;
delay5s <= ‘0’;
end if;
end if;
end if;
end process;
end arch;
Related Questions
drjack9650@gmail.com
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.