q12 12) A four-state FSM design has been handed down to a new digital design eng
ID: 2250261 • Letter: Q
Question
q12
12) A four-state FSM design has been handed down to a new digital design engineer with a partial schematic. The desired state diagram of the FSM is known, and the excitation functions of the two FFs are known, but the type of FFs to be used was not recorded. At least it is known that they must be T or D FFs because they only have one excitation function each. The excitation functions are where x is the primary input and y,Vo are the state variables. Determine which FFs or combination of FFs can be used to implement the specified state diagram. 10 0,1 FF0 01 CLK A. FFO: T; FF1: T B. FFO: D; FF1: D C. FFO: T; FF1: D D. FFO: D; FF1:T E. None of the above; erroneous excitation logicExplanation / Answer
Solution:
The given problem is solved by obtaining state table and input values for each combination of present state and inputs. The state table is given here,
Present state
Input
Input to FFs
Next State
Y1
Y0
x
E1
E0
Y1+
Y0+
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
0
0
1
0
0
1
1
1
1
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
0
From the state table, E1 is same as that of the Y1. So, FF1 is a D-Flip flop because the input is same as the next state it means that the input is propagated to output with clock edge.
From the state table, present state is same as next state, when the E0 (input to the Flipflop) is low and
present state toggles that is equal to the next state, when the E0 (input to the Flipflop) is high. S0, FF0 is a T Flip Flop.
FF1 - D Flip-flop
FF0 - T Fip-flop.
Option (C) is correct.
Present state
Input
Input to FFs
Next State
Y1
Y0
x
E1
E0
Y1+
Y0+
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
0
0
1
0
0
1
1
1
1
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
0
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