Trace the execution of the 4-bit sequential multiplier shown in Figure 6.65 when

Question

Trace the execution of the 4-bit sequential multiplier shown in Figure 6.65 when the multiplier is 5 and the multiplicand is 10 by following the FSM shown here. (Note that this is the same FSM that is shown in Figure 6.66 except that the states are named.)

a. What are the contents of all 3 registers in state B?

b. Will the multiplicand or multiplier registers change before the controller returns to state A?

c. What will be the sequence of states for the operation in this problem (multiplier = 5 and multiplicand = 10)?

d. For each of states CK in the sequence listed in part c, show what happens to the contents of the running sum register and why.

multiplier multiplicand multiplicand register (4) load mdld 4-bit adder multiplier register (4) mrid load mr3 mr2 mr1 mro rsclear rsshr load clear running sum shr register (8) start product Figure 6.65 Internal design of a 4-bit by 4-bit sequential multiplier

Explanation / Answer

Pre Calculation,

Here we have given multiplicand(md) 10(1010 in binary) and Multipliar(mr) 5(0101 in binary).

Now we need 8 bit storage to store answer for 4 bit multiplier. That's why we have 8 bit running sum register (Just for Info :-) ).

Let's solve our problem,

a) What are the contents of all 3 registers in state B?

To go from state A to B, We have just inserted the START and till this state we have mdld, mrld and rsclear are 0. So all three registers are 0.

b. Will the multiplicand or multiplier registers change before the controller returns to state A?

Carefully observe Multiplicand and Multiplier registers here we only have load signal and from the state diagram if you observe than we are just returning after four right shifts. So No both registers will not change before the controller returns to state A.

c. What will be the sequence of states for the operation in this problem (multiplier = 5 and multiplicand = 10)?

Here we have multiplier = 5 and binary sequence for 5 is 0101.

Now, Seq. for this multiplier is A->B->C->D->E->G->H->I->K->A

Why, After inserting signal start State will change from A to B and After inserting all load signals state will change from B to C.

Now (mr3,mr2,mr1,mr0) = (0101).

for mr0 = 1 state will change to D and than in next cycle it will change to E.

for mr1 = 0 state will change directly to G.

for mr2 = 1 state will change to H and than in next cycle it will change to I.

for mr3 = 0 state will change to K and than to A.

so, A->B->C->D->E->G->H->I->K->A

d. For each of states CK in the sequence listed in part c, show what happens to the contents of the running sum register and why.

For state C content of summing register is 0000 0000.

Now observe 4 MSB(most significant bits) of this register are fedback to adder and 4 LSB are fed back to it self.

mr0 is 1 so state will change from C->D and in D rsload = 1 so for rsload = 1 answer for given configuration is

1010 0000.

Because we are adding 1010 with 0000 in adder and loading this into MSBs of SR(Summing Regoster).

In next stateE we are right sifting the content of SR so answer for SR = 0101 0000.

for state G we are again right shifting content of SR, So answer for SR = 0010 1000

for state H we are loading content of adder into the MSB. for this cofiguration we have A = 1010(Multiplicand) and B = 0010(MSBs of SR).

Sum for given number is 1100.

so, content of SR = 1100 1000

for state I we are shifting SR one bit So, SR = 0110 0100

for state K we are again shifting SR one bit SR = 0011 0010

So, The final answer for given values is 0011 0010 which is nothing but 50 (10*5).

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