Name I. The sum of veltages in a single loop going clockw D (F) (D (0) T (F) kwi
ID: 2265762 • Letter: N
Question
Name I. The sum of veltages in a single loop going clockw D (F) (D (0) T (F) kwise is zero e sum of currents entering a node is equal to the sums of eu rrents leaving 3. You must have a reference node in nodal analysis 4. In nodal analysis the reference sode has a voltage of zero S. Three essential nodes means twe nodal equations to solve hree meshes means, in general, three mesh equations to solve 7. To make a voltage source zero you 8. To make a current source zero you open it 9. In an induetor, the voltage is proportional to the derivative of current 10. In a capacitor, the current is proportional to the derivative of the voltage (F) (T) (F (T (F short it 11. Two branches in parallel must have different voltage 12. It is true that I -R/V (T 13. In Phasor Domain, circuit elements cannot be combined in series like resistors D (F) 14. At high frequency the inductor has low impedance 15. At high frequency the capacitor has high impedance 16. In voltage divider circuit, RI and R2 are in parallel (T) (F 17. In current divider circuit, R1 and R2 are in series 18. The maximum output voltage can exceed the input voltage in RLC eireuits 19. A low pass filter passes high frequencies below cutoff (T) (E 20. A high pass filter passes frequencies below cutoffExplanation / Answer
1. True- Kirchoff voltage law
2. True- Kirchoff current law
3. True
4. True
5. True if third node is ground node
6. True
7. True
8. True
9. True v=l(di/dt)
10. True i=c(dv/dt)
11. False. Voltage across all parallel branches are same
12. False. I= V/R by ohms law
13. False.
14. False. XL=jwL. At high frequency impedance is high
15. False. XC=1/jwC. At high frequency impedance is zero
16. False. They are in series
17. False. They are in parallel
18. False
19. False- it passes high frequency below cut off
20. False . High pass filters does not pass any frequency below cut off
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