1) The \"with/select\" selected signal assignment offers an alternative to the C
ID: 2265878 • Letter: 1
Question
1) The "with/select" selected signal assignment offers an alternative to the Case statement. Unlike Case, with/select does not go in a process, so it is quicker to write. Being outside the process it must be kept simple (no nesting for example). The code below makes "101" when ADDR-"OI" or "10", Z-"111" when ADDR-"11" and Z-"000" for all other ADDR values (ADDR "00"). Rewrite the VHDL code replacing the "with/select" with a Case statement. library IEEE use IEEE.STD LOGIC_1164.ALL entity hw12 p1 is Port (signal ADDR: in STD LOGIC VECTOR(1 DOWNTO0) signal Z :out STD LOGIC VECTOR(2 DOWNTO O)) end hw12,p1 architecture behavioral of hw12 p1is begin outside all processes with ADDR select Z"101" when "01" | "10" "111" when "11" "000" when others; end behavioralExplanation / Answer
----------VHDL CODE------------
--now we are going to replace with select by case statement
library IEEE;
use IEEE.std_logic_1164.all;
entity hw12_p1 is
port( ADDER:in std_logic_vector(1 downto 0); --declare input variable name and size
Z:out std_logic_vector(2 downto 0)); --declare output variable name and size
end hw12_p1;
architecture behavioral of hw12_p1 is
begin
process(ADDER) --case works in processs only
begin
case ADDER is --check the value with ADDER || replacing with ADDER select with case
when "01"|"10" => Z<="101"; --here we can do other operations also not only restricted to single variable
when "11" => Z<="111";
when others =>Z<="000";
end case;
end process;
end behavioral;
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