The following are general questions about Hardware design, HDLs, Language based

Question

The following are general questions about Hardware design, HDLs, Language based tools and IDE’s: Be sure to mark all correct choices with a X and don’t circle so I can grade with a template!

A. Language based hardware design tools have a number of advantages: Check True or False for each listed possible advantage:

T    F    1)   Very complex designs can easily be done with gate level schematics

T    F    2) Language based tools allow for the design to be done at a behavioral level of abstraction

T    F    3) Language based tools make designs much easier to re-use

T    F    4) Vivado is a good example of a language based tool

T    F    5) Language based tools can allow designs to be simulated even before synthesis

B. Integrated Development Environments like Vivado contain the following features:

T    F    6) The ability to use modules written in different languages in the same project

T    F    7) The ability to simulate you system at different levels of abstraction and pre and post synthesis

T    F    8) Automatic Debuggers to fix behavioral errors in the code

T    F    9) Powerful text editors that check syntax and show key words automatically

T    F    10) A synthesizer that can create a “bit” file to program the FPGA   

C. The following are statements about hardware design. Mark ones that are in general true.

T    F    11) The re-usability of language based designs has been key in developing very complex IC’s

T    F    12) The HDL’s can be used to design both integrated circuits and implementations for FPGA’s

T    F    13) One of the keys to good design is to combine as much detail as possible in the Top module

T    F    14) There are several HDL’s including Verilog, VHDL, and System VHDL

T    F    15) Verilog is the most used HDL for fabrication in the US and Europe

D. General differences in writing good HDL code and C++ code are the topic of the next group

T    F    16) Verilog is more permissive than VHDL especially in always blocks compared to process blocks

T    F    17) You can write legal HDL code that cannot be synthesized

T    F    18) The magic in language based hardware design is in the text editor

T    F    19) The progress in synthesizers has driven most of the advances in language based designs

T    F    20) One great feature is the availability of lots of existing IP that can be imported to a new design

The following Questions are about Verilog HDL

E. The following refer to Verilog use in hardware design and what is not synthesizable:

T    F    21) Inertial delays cannot be synthesized

T    F    22) Propagation delays can be synthesized

T    F    23) “wait for 100ns” in an always loop can be synthesized

T    F    24) The “$display” operator is not synthesizable

T    F    25) Operators for addition, subtraction and multiplication can all be synthesized but not division

F. The following code segment be used for several questions.

module shift_reg #(parameter width=8) (

input reset_n, //reset async active low

input clk, //input clock

input data_ena, //serial data enable

input serial_data, //serial data input

output reg [width-1:0] parallel_data //parallel data out

);

always @ (posedge clk, negedge reset_n)

if(!reset_n) parallel_data <= '0; //could not do "width'd0"

else if (data_ena)

parallel_data <= {serial_data, parallel_data[width-1:1]};

endmodule

T    F    26) When you instantiate this module can you specify a different size shift register?

T    F    27) This is a “Shift Left” shift register

T    F    28) If you don’t specify a value for “width” it will equal 16 bits

T    F    29) This shift register can’t shift unless reset_n goes low

T    F    30) If you instantiated this same module twice, could you use a different size for width each time

31) Look at this instantiation:

“shift_reg #(16) SR1 (Rst, CLK, Enable, Data_in, Load_data);”

Mark the correct equivalent depiction of the variable “parallel_data” that would be used in the module:

reg [15:0] parallel_data     wire [16:0] parallel_data         reg[8:0] parallel_data       reg[7:0] parallel_data

G. This code segment will be used for several questions

module First_Mod(A, B, C, D);
input reg [3:0] A, B;

output [4:0] C;
always @ (A) begin
#5 A <= A + 1;
    C <= A + 1;

#5 B   = B + 1;
     C   = B + 1;

end
endmodule

A=      B=     C=    D=        32) A goes 2 to 3 and B= 0 is not changed Write the resulting values

Blocking   Non-Blocking    33) The statements in the procedural block for A and C are:

A=     B=     C=    D=        34) A goes 2 to 3 and B goes 3 to 4.   Write the resulting values

A=     B=     C=    D=        35) A=0 is not changed and B goes 3 to 4.   Write the resulting values

H. Answer the questions about the implications of these pushbuttons to this Spartan FPGA assuming that the buttons are normally open, momentary closed buttons. There are some settings that are required for these buttons to work. Note: Assume this FPGA works like the Artrix-7 we used

1.8V        2.5V         3.              36) You would need to set the bank for pins P29-33 to the right voltage

none    pull-ups    pull-downs 37) What other internal setting can you imagine might be required?

0          1                                    38) When the button is not pressed, what should the pin read?

_______________________    39) When the circuit was built and SW1 was pushed each time there was a defect on a conveyor belt to mark a defective product, sometimes several good products were also marked after the bad one as defective. What do you think might be causing this problem. (Hint: Remember a button is a mechanical device and the FPGA is very fast) :

40)   When you design with a Xilinx FPGA, what provision do you need to make on the Printed Circuit board that will mount the FPGA to allow it to function when you turn it on? (Assuming your code is good and all the pins hooked up correctly and all clocks and power set up correctly and board made right)

___________________________________________________________________________________

I. Consider the following:   (10 pts)

always @(s1, s0, i0, i1, i2)
case ({s1, s0})
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
endcase

41) What problem will be encountered with this code that was likely not intended? (X the p )

pwill create a 4:1 MUX              pwill create a combinational circuit            pwill create a latch

42) You can change the code and fix the result be including the following line: (check all that are true)

p2’d3 : out = 0;       p2’d3 : out = i3;        p default : out = 0;      p3’d4 : out = i4;

43) Would the following line fix the code also? 2’d3 : out = 1;        Yes      No

44) If you create a sub module and include it in the same file as the top level module but it is not instantiated in the top level module and there are no external port signals in the sub module, how will the synthesizer use this module?

pIt will function normally      pIt will not function at all      pIt might function normally

J. Look at these lines of code. Answer the questions:

            `timescale 1 ns / 10 ps

#5 a = b;  

c = #5 b;

45) What kind of delay does the second line show? (circle)  

Propagation Delay     Transport Delay     Inertial Delay     Blocking Delay

46) Would a and c be updated at the same time if b changes permanently from 0 to 1?   Y    N

47) What would happen to a if the signal b was initially 0 then 1 for 700 ps and then back to 0? (circle)

go to 1 for 700 ps and then back to 0      go to 1 at 5 ns and stay at 1    stay at 0    go to 1 at 5 ns and back to 0 at 10 ns

48) What would happen to c if the signal b was initially 0 then 1 for 700 ps and then back to 0? (circle)

go to 1 for 700 ps and then back to 0      go to 1 at 5 ns and stay at 1    stay at 0    go to 1 at 5 ns and back to 0 at 10 ns

K. A 2 input AND gate and OR gate inputs are 1 and X as the 2 inputs.

49) What is the output of the AND gate?   1        0         X        Can’t Specify

50) What is the output of the OR gate?    1        0         X        Can’t Specify

51) Write the code for a 2:1 MUX using a single statement:   use inputs I0 and I1 and select line as A

(don’t worry about any other code, just use 1 line, make I0 selected when A=0)

Explanation / Answer

A.
1. F (gate level schematics are not used to design complex designs)
2. T (Language based tools allow for the design at behavioral level)
3.T (language based tools makes designs to reuse)
4. T (but there are other good examples also)
5.F (designs can be simulated only after synthesis)

B.
6.F (different languages modules can't be used in same project)
7.T (simulation can be done at different levels)
8.T(debuggers are automatic)
9.F (not so powerful text editors)
10.T (synthesizer to create a bit file to program FPGA)

C.
11.T (it is the key feature)
12.T ( HDL can be used for both)
13.F (do not combine as much as possible)
14.T ( there are several)
15.T (verilog is mostly used)

D.
16.T (verilog is way more permissive than VHDL)
17.F (it can be synthesized)
18.F(text editor is important but is not magic)
19.T (synthesis is important so the progress definitely helps)
20.F (reuse of IP is done mostly)

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