and and are 25) The asynchronous inputs to a flip-flop are normally labeled norm
ID: 2266271 • Letter: A
Question
and and are 25) The asynchronous inputs to a flip-flop are normally labeled normally active inputs. A) START, STOP, low C) SET, RESET, high B) PRE, CLR, low D) ON, OFF, high flip-flops. 26) 26) Pulse-triggered flip-flops are also called D) level A) edge B) master-slave C) postponec 27) 27) Which of the following best describes the action of puise-triggered flip-flops? A) A pulse on the clock transfers data from input to output B) The synchronous inputs must be pulsed. C) The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock. D) The clock and R-S inputs must be pulse shaped. 28) 28) When both inputs of a J-K pulse-triggered FF are high, and the clock cycles, the output will A) not change C) be invalid B) remain unchanged D) toggle 29) 29) The L in 74L71 stands tor-- A) lock-out flip-flop C) the type of package B) low frequency D) low power 30) Which of the following is a primary characteristic of the data lock-out flip-tlop? A) Data is only clocked into the FF on the clock transition. B) Data can only be entered when the clock is high. C) Data cannot be entered into the FF unless the EN line is high. D) The master section is a pulse triggered type FF 31) 31) Which of the tollowing ratings is not associated with flip-flops? A) Hold time C) Set-up time 8) Propagation delay time D) interval time 32) Set-up time specifies A) the minimum time required tor the control levels to be maintained at the inputs of a tlip prior to the triggering edge of the clock in order for data to be reliably clocked into the component B) how long the operator has in order to get the flip-flop running before the maximum power level is exceeded C) the maximum time interval required for the control levels to remain on the inputs before the triggering edge of the clock in order for the data to be reliably clocked out of the FF D) how long it takes the output to change states after the clock has transitionedExplanation / Answer
25. B (Preset, Clear are normally async inputs available and they are active LOW)
26. B (Master-Slave)
27. C
28. D, output Q toggles
29. D, L stand for Low Power
30. A
31. D, Interval Time is not a standard definatiion in Timing related Sequential Logic designs
32. A
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