a) Log, Anti-Log and Summation circuit can be design to achieve signal multiplic
ID: 2266819 • Letter: A
Question
a) Log, Anti-Log and Summation circuit can be design to achieve signal multiplication, which is shown in Figure Q2a. Briefly, explain the working principles, and then identify its design limitation. (10) ANTILOG MULTIPLICATION Figure Q2a Multiplication by Diodes and Op. Circuits b) Signal multiplication can be achieved by so called brute force (8) method shown in Figure Q2b. What are its disadvantages in practice? V. digitalDIA multiplier V. Figure Q2b Multiplication by Digital Multiplier c) Figure Q2c below shows an analogue four quadrant multiplier. If transistors are matched, which is to say Q1 =Q2, Q3-Q4-Q5= Q, prove that (12) IoR 02 Vo1Explanation / Answer
2a). Multipliers based in the fundamental relationship that States product of two terms equal to sum of logarithm if each term.
ln(a*b)=ln a+ln b. It shows that 2 signal voltage are effectively multiplied if the logarithm of signal voltage added.
X*=log x, Y*= log y
After summation the equation becomes log x+log y= log(xy) and by applying antilogarithm function the output is exp( log xy) = xy
To get logarithm characteristics a BJT is connected as a diode because of this the logarithmic range limited to 4 or 5 decades as the current adds to collector current.
b )
Disadvantage of brute force method to implement multiplier :
To increase the sampling rate of ADC inorder to digitize input signal allowing RMS and a whole range of other function to be carried by a digital processor.
Digitizing the signal costs unreasonable amount of power due to need of high speed ADC.
Using digital circuit at lower frequencies will be good but as the frequency rises the cost of implementing digital circuit increases
Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.