3. 14 marks) In this assignment you will design an arithmetie logie unit (ALU) w

Question

3. 14 marks) In this assignment you will design an arithmetie logie unit (ALU) which can be used readily in a MIPS processor. In particular, we focus on the arithmetic logic instructions among MIPS R-type instructions. Each machine instruction in a MIPS processor has a 6 bit field called F(denoted briefly by F here). A MIPS coupatible ALU takes Fso as a control input. This control input determines the relation between the data inputs A and B, and the output Y as per Table 4, which is a part of the set of MIPS R-type instructions A step by step design process is described in the ecture slides. Note that the ALU hardware inclades an adder. For this assignment you are Eree to choose any adder implementatio including the behavioural one using System Verikg operator. (8 marks) Design an n bit wide parameterized ALU module as per Table 4. The ALU should have two additional outputs Cod and OV to flag the carry out and arithmetic overflow in arithmetic operations. (6 marks) Design an appropriate test-bench to sinnalate the functionality of your de- signed circuit on some simulator like Modelsim. 0000 A+ 0001 AB (unsigned addition) 0010 A-(signed subtraction) 00 A-B (unsigned subtraction) 0100 A& B (AND) 0101 AB (OR) 0110 | A eB (XOR) 0111 (AB) (NOR) 1010 | if(A

Explanation / Answer

i have dedigned this ALU code in XLINX VIVADO 2016.2 along with the test bench...the code is as follows

module all(
input a,
input b,
input cin,
input [3:0] f,
output y,
output cout,
output ov
);
reg y,cout,ov;
always@(f)
begin
if(f==4'b0000)
{cout,y}=a+b+cin;
else if(f==4'b0001)
{cout,y}=a+b+cin;
else if(f==4'b0010)
{ov,y}=a-b;
else if(f==4'b0011)
{ov,y}=a-b;
else if(f==4'b0100)
y=a&b;
else if(f==4'b0101)
y=a|b;
else if(f==4'b0110)
y=a^b;
else if(f==4'b0111)
y=~(a|b);
else if(f==4'b1010)
begin
if(a<b)
y=0;
else
y=a;
end
else if(f==4'b1011)
begin
if(a<b)
y=0;
else
y=a;
end
end   
endmodule

TEST BENCH:

I have written this test bench for checking 2 conditions that is when f=0000 and f=0101...if you want to check for all values of f just give the f values in always statement followed by a,b with some delay...it will be giving the all values as it is in truth table

module all_tb();
reg a;
reg b;
reg cin;
reg [3:0]f;
wire y;
wire cout;
wire ov;
all UUT(a,b,cin,f,y,cout,ov);
initial
begin
f=4'b0000;a=1'b0;b=1'b0;cin=1'b0;
end
always
begin
#5 f=4'b0001;a=1'b1;b=1'b1;
#5 f=4'b0101;a=1'b1;b=1'b1;
end
endmodule

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