SER IN K DO DI D2 D3 SH/LD SER IN K SHLD CLR D0- Di D2 SRG4DO Q2 Figure 9-4 Kefe

Question

SER IN K DO DI D2 D3 SH/LD SER IN K SHLD CLR D0- Di D2 SRG4DO Q2 Figure 9-4 Keferring to Figure 9-4, what action takes place during the period marked 'W' on the timing diagram? 32) A) The register has gone into the counter mode and is counting the value of the parallel data previously stored on the parallel inputs. B) The register has just been cleared and the clock pulses are being toggled through the register. C) The data is shifted from the parallel inputs to the parallel outputs. D) Data is being serially shifted through the register 33) Referring to Figure 9-4, at point X'on the timing diagram, what action will take place? A) The inputs will be disabled B) All inputs and outputs will be reset to LOW C) The outputs will all go LOW. D) Only the CLK will be disabled during this time, preventing any transfer of data between inputs and outputs

Explanation / Answer

For question no 32

Option d data is being serially shifted through the register

When sh/ld- is low the data from input is loaded to registers and after next positive edge data are serially shifted through the registers

For question no 33

Option b All the inputs and outputs will be low

Clear input is low all the inputs and outputs will be reset to low

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