Verilog: alu.v //32-bit ALU //To get all scores, you cannot use arithmetic opera

Question

Verilog:
alu.v

//32-bit ALU
//To get all scores, you cannot use arithmetic operators in this module.
module ALU(
       input [31:0] a,
       input [31:0] b,
       input [2:0] op,
       output reg [31:0] s);
//write your code here
endmodule

ALU Implement a 32-bit ALU Input: a (32 bits), b (32 bits), and op (3 bits). Output: s (32 bits). The ALU should send the results of operations with a and b to s. The operations are specified by the value of op, as shown in the following table: Assume a = 0:0000001 and b = 0xFFFFFFFF. Table 3: Operations of ALU op operation 0 a+ b 0x00000000 a -b 0x00000002 2a +1 0x00000002 0x00000000 a AND b 0x00000001 5 a OR b 0xFFFFFFFF a XOR b 0xFFFFFFFE 7NOT a 0xFFFFFFFE 0 we also show the results of each operations in the above table. Notice that AND,OR, XOR, and NOT operations are bitwise operations Notice that you cannot use arithmetic operators (including +, -, *, / , ** , %) in Verilog in this module, but logical and bitwise operators are allowed.

Explanation / Answer

module fulladder (
  input A,
  input B,
  input Cin,
  output Sum,
  output Cout
);

assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (A & Cin) | (B & Cin);

endmodule

module adder_subtractor
#(parameter WIDTH = 32)
(
  input [WIDTH-1:0] A,
  input [WIDTH-1:0] B,
  input Cin,
  output [WIDTH-1:0] Sum,
  output Cout
);

wire [32:0] w;

assign w[0] = Cin;

genvar i;
generate
for(i = 0; i < WIDTH; i = i + 1)
begin : FULL_ADDER
   fulladder U (.A(A[i]), .B(B[i]), .Cin(w[i]), .Sum(Sum[i]), .Cout(w[i+1]));
end
endgenerate

assign Cout = w[32];

endmodule


module ALU (
input [31:0] a,
input [31:0] b,
input [2:0] op,
output reg [31:0] s
);

wire [31:0] a_add, b_add, s_add;
wire w1, w2;

assign a_add = a;
assign b_add = (op[1] ? 32'b1 : (op[0] ? ~b : b));
assign w1 = op[0];

// For arithmetic operations we are using adder_subtractor module
adder_subtractor full1 (.A(a_add), .B(b_add), .Cin(op[0]), .Sum(s_add), .Cout(w2));

always @ (*)
  begin
   s = 32'd0;
   case(op)
   3'd0 : s = s_add;
   3'd1 : s = s_add;
   3'd2 : s = s_add;
   3'd3 : s = 32'd0;
   3'd4 : s = a & b;
   3'd5 : s = a | b;
   3'd6 : s = a ^ b;
   3'd7 : s = ~a;
   endcase
  end
endmodule




module testbench_ALU;

reg [31:0] a, b;
reg [2:0] op;
wire [31:0] s;

ALU m1 (.op(op), .a(a), .b(b), .s(s));

integer i;

initial
  begin
   $monitor("op = %d a = %b b = %b, s = %b", op, a, b, s);

   a = 32'd64;
   b = 32'd15;
   for (i = 0 ; i < 8 ; i = i + 1) begin
   op = i; #10;
   end

   a = 32'd254;
   b = 32'd239;
   for (i = 0 ; i < 8 ; i = i + 1) begin
   op = i; #10;
   end

  end

endmodule

/**************************** Simulation Result ********************************
op = 0 a = 00000000000000000000000001000000 b = 00000000000000000000000000001111, s = 00000000000000000000000001001111
op = 1 a = 00000000000000000000000001000000 b = 00000000000000000000000000001111, s = 00000000000000000000000000110001
op = 2 a = 00000000000000000000000001000000 b = 00000000000000000000000000001111, s = 00000000000000000000000001000001
op = 3 a = 00000000000000000000000001000000 b = 00000000000000000000000000001111, s = 00000000000000000000000000000000
op = 4 a = 00000000000000000000000001000000 b = 00000000000000000000000000001111, s = 00000000000000000000000000000000
op = 5 a = 00000000000000000000000001000000 b = 00000000000000000000000000001111, s = 00000000000000000000000001001111
op = 6 a = 00000000000000000000000001000000 b = 00000000000000000000000000001111, s = 00000000000000000000000001001111
op = 7 a = 00000000000000000000000001000000 b = 00000000000000000000000000001111, s = 11111111111111111111111110111111

op = 0 a = 00000000000000000000000011111110 b = 00000000000000000000000011101111, s = 00000000000000000000000111101101
op = 1 a = 00000000000000000000000011111110 b = 00000000000000000000000011101111, s = 00000000000000000000000000001111
op = 2 a = 00000000000000000000000011111110 b = 00000000000000000000000011101111, s = 00000000000000000000000011111111
op = 3 a = 00000000000000000000000011111110 b = 00000000000000000000000011101111, s = 00000000000000000000000000000000
op = 4 a = 00000000000000000000000011111110 b = 00000000000000000000000011101111, s = 00000000000000000000000011101110
op = 5 a = 00000000000000000000000011111110 b = 00000000000000000000000011101111, s = 00000000000000000000000011111111
op = 6 a = 00000000000000000000000011111110 b = 00000000000000000000000011101111, s = 00000000000000000000000000010001
op = 7 a = 00000000000000000000000011111110 b = 00000000000000000000000011101111, s = 11111111111111111111111100000001
*******************************************************************************/

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