2. An engineer is going to solve a combinational logic design problem by using a

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2. An engineer is going to solve a combinational logic design problem by using a ROM The circuit is to have two 4-bit nmbers X (xxxx) and Y (yyyy). It is to add the mumbers and provide a 4-bit result In adäition it is to have two adoitional outputs: one to indicate overflow if the rumbers are 4-bit unsigned irtegers and one to indicate overflow if the mumbers are 4-bit two's complement integers. Note that the 4-bit sum will be the same in either mmber system) Thus the circuit has s inputs and outputs. The 8 inputs are to be connected to the 8 address inputs of the ROM (A- to Ao) as follows There are 6 data outputs of the RONA D, to Du which are comnected to the circuit outguts as follows D, to D are the 4-bit sum, with D, the MSB (most significant bit), D is umsigned integer overflow, and Do is tmo's complement overflow. adresses X data bita address, AND by total ber a) That size ROM is needed? Specify by of hits Do not use approximations.) b) Assuming that the cormections are as described above, determine the ROM contents of the addresses 2sked for in the table below. Use binary for the contents. to to

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kindly re-upload the picture as the text are not clear and making it hard to understand the question.

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