Q1) Design an 8-1 Multiplexer A multiplexer is a device that selects one of seve
ID: 2290937 • Letter: Q
Question
Q1) Design an 8-1 Multiplexer A multiplexer is a device that selects one of several analog or digital input signals and forwards the selected input into a single output line. A multiplexer of 2" inputs has n select lines, which are used to select which input line to send to the output. For this part, design an 8-1 multiplexer that selects one out of the eight 4-bit inputs and transmits this 4-bit value to the output. Please use if-then-else statement to setup your multiplexer Please design the entity as well as the test bench for this 8- to-1 multiplexer Your entity design is: Your test bench design is: r test bench design, please enable each one of the 4 In you inputs at one time. For example enable 10 to go through the multiplexer first. Please set 10 to be at "0000" for 50ns, and then "?00l" for 50ns. After that enable II (go through"0010" and "0011"), 12 (go through "0100" and "0101"), 13 (go through "0110" and "0", 14 (go through "1000" and “1001"), 15 (go through .. 1010" and .. 1011"), 16 (go through "1100" and 01") and 17 (go through "1110" and "") correspondingly The result waveforms are: Please select the signals to be simulated in the following order: Sel, 17, 16, 15, 14, 13, 12,, I0, Out.Explanation / Answer
library ieee;
use ieee.std_logic_1164.all;
entity mux8x1_design is
port (
I0, I1, I2, I3, I4, I5, I6, I7 : in std_logic_vector(3 downto 0);
Sel2, Sel1, Sel2 : in std_logic;
Out1 : out std_logic_vector(3 downto 0)
);
end mux8x1_design;
architecture behavioural of mux8x1_design is
signal temp_sel : std_logic_vector(2 downto 0);
begin
temp_sel <= Sel2 & Sel1 & Sel0
process (I0, I1, I2, I3, I4, I5, I6, I7, temp_sel)
begin
if (temp_sel = "000") then
out1 <= I0;
elsif (temp_sel = "001") then
Out1 <= I1;
elsif (temp_sel = "010") then
Out1 <= I2;
elsif (temp_sel = "011") then
Out1 <= I3;
elsif (temp_sel = "100") then
Out1 <= I4;
elsif (temp_sel = "101") then
Out1 <= I5;
elsif (temp_sel = "110") then
Out1 <= I6;
else
Out1 <= I7;
end if;
end
end behavioural;
library ieee;
use ieee.std_logic_1164.all;
entity mux8x1_design_tb is
end mux8x1_design_tb;
architecture testbench of mux8x1_design_tb is
component mux8x1_design
port (
I0, I1, I2, I3, I4, I5, I6, I7 : in std_logic_vector(3 downto 0);
Sel2, Sel1, Sel2 : in std_logic;
Out1 : out std_logic_vector(3 downto 0)
);
end component;
signal I0, I1, I2, I3, I4, I5, I6, I7, Out1 : std_logic_vector(3 downto 0):="0000";
signal Sel2, Sel1, Sel0 : std_logic := '0';
begin
DUT1 : mux8x1_design port map ( I0, I1, I2, I3, I4, I5, I6, I7, Sel2, Sel1, Sel0, Out1);
process
begin
Sel2 <= '0'; Sel1 <= '0'; Sel0 <= '0';
I0 <= "0000" wait for 50 ns;
I0 <= "0001" wait for 50 ns;
Sel2 <= '0'; Sel1 <= '0'; Sel0 <= '1';
I1 <= "0010" wait for 50 ns;
I1 <= "0011" wait for 50 ns;
Sel2 <= '0'; Sel1 <= '1'; Sel0 <= '0';
I2 <= "0100" wait for 50 ns;
I2 <= "0101" wait for 50 ns;
Sel2 <= '0'; Sel1 <= '1'; Sel0 <= '1';
I3 <= "0110" wait for 50 ns;
I3 <= "0111" wait for 50 ns;
Sel2 <= '1'; Sel1 <= '0'; Sel0 <= '0';
I4 <= "1000" wait for 50 ns;
I4 <= "1001" wait for 50 ns;
Sel2 <= '1'; Sel1 <= '0'; Sel0 <= '1';
I5 <= "1010" wait for 50 ns;
I5 <= "1011" wait for 50 ns;
Sel2 <= '1'; Sel1 <= '1'; Sel0 <= '0';
I6 <= "1100" wait for 50 ns;
I6 <= "1101" wait for 50 ns;
Sel2 <= '1'; Sel1 <= '1'; Sel0 <= '1';
I7 <= "1110" wait for 50 ns;
I7 <= "1111" wait for 50 ns;
end process;
end testbench;
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