Given the plant shown below, analytically design a controller to yield zero stea

Question

Given the plant shown below, analytically design a controller to yield zero steady-state error for a step input, a

2% settling time of 1 second, 10% overshoot, a gain margin greater than 6 dB, and a phase margin greater than 30 degrees.

You must show the analytical process and all steps you took to design your controller.

Use MATLAB/Simulink to simulate the system and your feed-back controller for a unity step input R(s). Provide the time domain plot of Y(s) from 0s ? t ? 5s.

Explanation / Answer

run this code :

clc;
close all;
clear all;
s =tf('s');
G = 10/(s+2) ;
% to yield zero ss error lets use an itegrator
%zeta*wn = 4/1 = 4
OS= 0.1 % 10% overshoot
a = log(1/OS) ;
zeta = a/sqrt(a^2+pi^2);
wn = 4/zeta ;
ce = s^2 + 2*zeta*wn*s + wn^2 ;
% ce = 1+GC
s1= -2*zeta*wn + wn*sqrt(1-zeta^2);
s2= -2*zeta*wn - wn*sqrt(1-zeta^2); %%required ones
% both lying in neg half of s plane
bode(G)
C = 4*(s+2)/s ;
L = G*C ; %% if possible try always to get L shape as an integrator
margin(L);
T = L/(1+L);
pole(T);
figure(1)
subplot(2,1,1);
margin(L);
subplot(2,1,2);
step(T)
%% to get time upto 5 sec run the code, double click on the step response
%% then limits--> x axis set it to 5 sec.

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