6. Consider an in-order 5-stage pipeline similar to the one discussed in class,

Question

6. Consider an in-order 5-stage pipeline similar to the one discussed in class, e.g, see slides 4.6of lesture 18 e First assume that the pipeline does not support bypassing (forwarding) Whot are the stall cycles introduced between the following pairs of back-to-back instructions? Then, solve the same problem while assuming support for bypassing Clearly show your work, le, show how each instruction gol through the 5 stages, indicate the point of production and point of consumption, show how the consuming instruction D/R stage when there are stalls. Recall that a register read is performed in the second half of the D/R stage and a register write is performed in the first half of the RW stage. (30 points) 1. lw $1. 8152) add $4, $1. $3 sw $3, 803 1)

Explanation / Answer

1. lw $1, 8($2)
add $4, $1, $3

without forwading

       1   2 3 4 5 6 7 8

lw $1,8($2) IF D/R ALU DM RW

add $4,$1,$3 IF STALL STALL D/R ALU DM RW

  
operands ($1,$3) are available only at the end of first half of RW stage

with forwarding
  
       1   2 3 4 5 6 7 8

lw $1,8($2) IF D/R ALU DM RW

add $4,$1,$3 IF D/R STALL ALU DM RW

Here at 4th clock cycle, the effecctive address at ALU stage and loads it in DM stage

In 5th clock cycles , operand is available.

2. lw $1, 8($2)
sw $3, 8($1)

without forwarding

       1   2 3 4 5 6 7 8 9 10

lw $1,8($2) IF D/R ALU DM RW

sw $3,8($1) IF STALL STALL D/R ALU DM RW   

only at 5th clock cycle, $1 is available.

  
with forwarding
  
       1   2 3 4 5 6 7 8 9 10

lw $1,8($2) IF D/R ALU DM RW

add $4,$1,$3 IF D/R STALL ALU DM RW

At 4th clock cycle, $1 is loaded. To store the value of $3 to 8($1) we have to wait till $1 is loaded with new value. after that thee value is directly forwarded to ALU unit if SW instruction.

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