(TCO 5) With a 1 MHz clock frequency, 8 bits can be serially entered into a shif

Question

(TCO 5) With a 1 MHz clock frequency, 8 bits can be serially entered into a shift register in _____.

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Question 25 pts

(TCOs 1 and 5) A shift register is described in VHDL with: Q(3 DOWNTO 0) <= Q(2 DOWNTO 0) & D. This register has which configuration?

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Question 35 pts

(TCO 6) How many bubbles are required in a state diagram to fully describe the operation of a MOD-25 counter?

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Question 45 pts

(TCO 6) When using a Mealy-type state machine, what signal or signals control a conditional transition between states?

Explanation / Answer

1) 8 µsec

nTs =n/fs = 8/1*106 = 8 µsec

2) Serial-in parallel-out

3) 32

A state diagram uses bubbles to represent each of the unique circuit states and arrows connectingthe states to indicate the sequence of operation.A MOD-25counter will be designed with 25 counts, but using 5 flip-flops will produce 25= 32 unique states

4)Inputs only

Inputs only signal can control a conditional transition between states when using a Mealy-type state machine

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