multiplier prod(9:0) (a) b(40)- multiplier Figure 5.16 Exercise 5.15: Recommende
ID: 2291434 • Letter: M
Question
multiplier prod(9:0) (a) b(40)- multiplier Figure 5.16 Exercise 5.15: Recommended Unsigned Multiplier Implementation Figure 5.16(a) shows a multiplier. Write a VHDL code that implements this circuit for an unsigned system. In the design, follow the recommendations presented in section 5.7. Exercise 5.16: Recommended Signed Multiplier Implementation Figure 5.16(a) shows a multiplier. Write a VHDL code that implements this circuit for an signed system. In the design, follow the recommendations presented in section 5.7.Explanation / Answer
5.15 ) Unsigned Multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity mult is
port(
a : in STD_LOGIC_VECTOR( 4 downto 0);
b : in STD_LOGIC_VECTOR( 4 downto 0);
p : out STD_LOGIC_VECTOR( 9 downto 0);
);
end mult;
architecture mult of mult is
begin
process(a,b)
variable pv,bp: STD_LOGIC_VECTOR( 9 downto 0);
begin
pv :="0000000000";
bp :="00000" & b;
for i in 0 to 4 loop
if a(i) = '1' then
pv :=pv + bp;
end if;
bp := bp(8 downto 0) & '0';
end loop;
p <= pv;
end process;
end mult;
5.16 ) Signed Multiplier :
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.PACK.all;
entity mult is
port(
a : in STD_LOGIC_VECTOR( 4 downto 0);
b : in STD_LOGIC_VECTOR( 4 downto 0);
p : out STD_LOGIC_VECTOR( 9 downto 0);
CP, RESET : in STD_LOGIC;
);
end mult;
architecture mult of mult is
begin
process(a,b)
variable a,b : INPUT_TYPE;
variable PROD : OUTPUT_TYPE;
begin
RESET_LOOP : loop
a := 0;
b := 0;
p <= 0;
a := IN1;
b := IN2;
wait until ( CP = '1' and CP'event);
if RESET = '1' then
exit RESET_LOOP;
end if;
MAIN_LOOP : loop
PROD := a * b;
p <= PROD;
wait until ( CP = '1' and CP'event);
if RESET = '1' then
exit RESET_LOOP;
end if;
end loop MAIN_LOOP;
end loop RESET_LOOP;
end process;
end mult;
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