14 pts) Suppose that a JSR instruction in LC-3 assembles as x4816 and the instru

Question

14 pts) Suppose that a JSR instruction in LC-3 assembles as x4816 and the instruction is located at x3306 in memory. What is the effective address of the corresponding subroutine? Justify 1. 2. 12 ptsj How many TRAP service routines may be implemented in LC-3? Why? 3. [2 pts] Can TRAP? Explain. a JMP R7 instruction be executed in lieu of a RET instruction in order to return from a 12 pts] How many accesses to memory are made during the execute phase of a TRAP instruction? Assume that the TRAP instruction is already in the instruction register(IR)

Explanation / Answer

Answer :- 1) The JSR instruction in LC-3 has following machine code format-

0100 1 PC_Offset_11_bit i.e. a 12-bit machine code. Now we have machine code as- 0x4816 in hexadecimal. In binary format it can be written as- 0100 1000 0001 0110. Out of these our 11-bit offset address is(in binary) -
000 0001 0110 i.e. 0x016.

Hence from current PC value i.e. 0x3306 we need to add 0x016 to get the subroutine address.

So the sub-routine address would be- 0x3306 + 0x016 = 0x331C .

Answer :- 2) LC-3 has 8-bit trap vector and hance it can support maximum 256 trap service routine.

Answer :- 3) Yes, JMP R7 can be used to return from TRAP service routine. R7 contains older PC value.

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