The ARMv7-M instruction set has a feature called \"conditional execution\" for i
ID: 2291569 • Letter: T
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The ARMv7-M instruction set has a feature called "conditional execution" for instructions. The ARM manual defines it as follows: Conditionally erecuted means that the instruction only has its normal effect on the programmers model operation, memory and coprocessors if the N, Z, C and V flags in the APSR [Application Program Status Register] satisfy a condition specified in the instruction. If the flags do not satisfy this condition, the instruction acts as a NOP, that is, execution advances to the next nstruction as normal cluding any relevant checks for exceptions being taken, but has no other effect Let me paraphrase. When an ARM implementation runs the instruction CMP, that sets a set of flags. Those flags together encode particular results of the comparison, such as equality or less- than. For the purposes of this question, those flags remain set until another CMP instruction is executed. Future instructions can be "conditally executed" based on the flags set by CMP: the programmer can designate a conditionally-executed instruction by appending a condition (such as EQ for equality or LT for less-than) to the opcode for that instruction. The conditionally- executed instruction only runs if the flags satisfy the designated condition. (Of course, if no condition is specified, the instruction runs unconditionally.) In ARM, branch instructions also use the result of CMP instructions (as opposed to MIPS, where BEQ both executes the comparison and branches based on it) As an example, consider the following code sequence that checks if r3 is zero and if not performs an add operation CMp r3, #0 BEQ skip // compare r3 to zero // if the previous CMP indicated equality, // jump to "skip" ADD r0, r1, r2 // r0 r1 r2 kip A clever ARM programmer can rewrite this using conditional execution: CMP r3, #0 ADDNE r0, ri, r2 // only if the previous comparison was compare r3 to zero // not-equal, compute ro rl r2 Note that ADDNE is an ADD instruction with the condition NE (not equal), where the condition was set on the previous CMP (comparison) operation. Other conditions that you may find useful: EQ (equal), GT (greater-than), and LE (less-than-or-equal) (a) (2 points) In one word, what is the concept we discussed in class that describes what we're doing when we conditionally exccute an ARM instruction? (b) (4 points) Name two advantages of adding conditional execution to an instruc- (e) (2 points) Name one potential disadvantage of adding conditional execution to (d) (5 points) Explain in English, completely but as briefly as possible) what the following tion set an instruction set ARM code does. You should need no more than one sentence. CMP r0 , #0 CMPNE r0 , #1 MOVEQ r1, #1 (Notes: # indicates an immediate value la constant]; MOV copies its second argument to its first argument; EQ indicates conditional execution if the previous CMP [comparison operation indicated the first argument is equal to the second; NE indicates conditional execution if the previous CMP comparison operation indicated the first argument is not equal to the second.) (e) (5 points) Using the operations CMP and MOV, and using conditional operations as appro- priate, write a segment of ARM code as succinctly as possible that implements the following If r0 is less than or equal to zero, set t to 0, otherwise set it to 1Explanation / Answer
(a)
We can execute an instruction conditionally based upon the ALU status flags set by another instruction, either:
immediately after the instruction that updated the flags
after any number of intervening instructions that have not updated the flags.
The instructions that you can make conditional depends on whether the processor is in ARM state or Thumb state.
To make an instruction conditional, you must add a condition code suffix to the instruction mnemonic. The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a conditional instruction fails, the instruction:
does not execute
does not write any value to its destination register
does not affect any of the flags
does not generate any exception.
(b)1-Reduce no. of branch instructions
2-The no. Of cycles resuces
(C) Use of more bits
(D) CMP r0, #0, if content of r0 is same as 0 then only the next instructions are executed.
CMPNE r0, #1, if content of r0 is not same as 1 then next lines are exevexec.
MOVEQ r1,#1, move1 to r1 register if Z(zero flag) is 0.
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