There are many other similar answers for my question on chegg, they dont fit my

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There are many other similar answers for my question on chegg, they dont fit my question Please do your own, dont copy and paste, thanks Design a 32 bit ALU use System verilog in Quartus, and simulate it in ModelSim The code starts with module alu(input logic [31:0] a, b, input logic [1:0] ALUControl, output logic [31:01 Result output logic [3:0] ALUFlags); And please design your ALU code follow by the schematic below ALU with Status Flags ALUControlo Suma1 ALUControl Sum 10 01 00 ALUControl Result31 o Verflow Carry Negative Zero Result ALUFlags More detail comments on your code would be appreciated

Explanation / Answer

module ALU #(parameter N = 32) ( // Without using + - * / % operators for arthimetic calculations
input logic [N-1:0] A,
input logic [N-1:0] B,
input logic [1:0] ALUControl,
output logic [N-1:0] Result,
output logic [3:0] ALUFlags);

logic [31:0] Bin, Sum, temp1, temp2;
logic Cout, temp3, temp4, N1, Z, C, V;

fulladder_Nbit #(.WIDTH(32)) ADD1 (.A(A), .B(Bin), .Cin(ALUControl[0]), .Sum(Sum), .Cout(Cout));

and_gate #(32) AND1 (temp1, A, B);
or_gate #(32) OR1 (temp2, A, B);

not NOT1 (ALUControlbar1, ALUControl[1]);
and AND2 (C, Cout, ALUControlbar1);
xnor XNOR1 (temp3, A[31], B[31], ALUControl[0]);
xor XOR1 (temp4, A[31], Sum[31]);
and AND3 (V, temp3, temp4, ALUControlbar1);

mux2x1 #(.N(32)) MUX1 (.I0(B), .I1(~B), .S(ALUControl[0]), .Y(Bin));
mux4x1 #(.N(32)) MUX2 (.I0(Sum), .I1(Sum), .I2(temp1), .I3(temp2), .S(ALUControl), .Y(Result));

assign N1 = Result[31];
assign Z = ~(|Result);
assign ALUFlags = {N1, Z, C, V};

endmodule

module and_gate #(parameter N = 1) (
  output [N-1:0] Y,
  input [N-1:0] A, B);

assign Y = A & B;

endmodule

module or_gate #(parameter N = 1) (
  output [N-1:0] Y,
  input [N-1:0] A, B);

assign Y = A | B;

endmodule


module fulladder (
  input A,
  input B,
  input Cin,
  output Sum,
  output Cout
);

assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (A & Cin) | (B & Cin);

endmodule

module fulladder_Nbit #( // N bit full adder
   parameter WIDTH = 4
) (
  input [WIDTH-1:0] A,
  input [WIDTH-1:0] B,
  input Cin,
  output [WIDTH-1:0] Sum,
  output Cout
);

wire [WIDTH:0] w;

assign w[0] = Cin;
assign Cout = w[WIDTH];

genvar i;
  generate
   for(i = 0; i < WIDTH; i = i + 1)
   begin : FULL_ADDER
   fulladder U (.A(A[i]), .B(B[i]), .Cin(w[i]), .Sum(Sum[i]), .Cout(w[i+1]));
   end
  endgenerate

endmodule

module mux2x1 #(parameter N = 1) (
  input [N-1:0] I0, I1,
  input S,
  output [N-1:0] Y);

assign Y = S ? I1 : I0;

endmodule

module mux4x1 #(parameter N = 1) (
  input [N-1:0] I0, I1, I2, I3,
  input [1:0] S,
  output [N-1:0] Y
);

assign Y = S[1] ? (S[0] ? I3 : I2) : (S[0] ? I1: I0);

endmodule

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