I need to add 7 segment decoder to the end of the most right shiftregister when
ID: 2291758 • Letter: I
Question
I need to add 7 segment decoder to the end of the most right shiftregister when the Top-Level entity is Block Diagram. The code and diagram are above, but it doesn't work and keep getting this error "Error: Width mismatch in port "S[3..0]" of instance "inst3" and type HEX_decoder -- source is ""Q" (ID shiftregister:inst18)". Please tell me what is wrong help me to fix it. Thanks.
librarY IEEE: use IEEE. STD LOGIC 1164.ALL use IEEE . STD LOGIC ARITH . ALL. use IEEE. STD LOGIC UNSIGNED.ALL; 7 entity HEX decoder is Port S: in STD LOGIC_VECTOR (3 downto 0) A : out STD LOGIC; B : out STD LOGIC; C: out STD LOGIC X : out STD LOGIC: E: out STD LOGIC: F out STD LOGIC; G : out STD LOGIC DP : out STD LOGIC); 10 12 13 14 16 17 18 19 architecture Behavioral of HEX decoder is 20 21 begin end HEX decoder: WITH S SELECT (A, B, C, X, E, F, G, DP) 23 24 25 26 27 28 29 30 31 32 std logic vector' (01100000) WHEN "0001", std_logic_vecto' "11011010") WHEN "oo1o", std_logic_vector'("11110010") WHEN "0011", std_logic_vector' ("01100110") WHEN "0100", std logic vector' ("10110110") WHEN "o10l" std_logic_vector'("11100100") WHEN "1li, 34 35 36 37 38 39 40 41 42 std_logic_vector' ("11110110") WHEN "1001", std logic vector' (11101110") WHEN "1010", std-logic-vector' ("00111110") WHEN "1011",1 std_logic_vector'("10011100") WHEN "1100, std logic vector' (01111010" WHEN "1101", std_logic vector' ("10011110") WHEN "1110" std_logic_vecto' ("10001110") WHEN i111", std logic vector' ("00000001" WHEN OTHERS: end Behavioral:Explanation / Answer
As per the diagram, you are trying to display data on seven segments. the problem with the code is that you are connecting the shift register output to hex decoder. The output of shift register (Q) is only ONE bit while the input for the hex decoder (S) is 4-bit.
This the meaning of Width mismatch error in your VHDL code. You Should check your shift register output to make it 4-bit or use the bit D0, D1, D2 and Q as input for Hex decode (if they are fulfilling the function of the block diagram)
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