please help solve 3 Q3. Figure 2 shows the timing diagram of a rising edge FF Da

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please help solve 3

Q3. Figure 2 shows the timing diagram of a rising edge FF Data input (dashed line) and clock input (solid line). The X-axis is in picoseconds. The FF requires 5ps of set-up time and 5ps of hold time. For each of the clock edge, indicate whether there are set-up or hold time violations. Indicate the time of the edge and circle one of Set-up violation, Hold violation, or None. (10 pts). Answers: (a) Clock edge 1:- (b) Clock edge 2:t- (c) Clock edge 3: t_ (d) Clock edge 4: t- (e) Clock edge 5: Sct-up Sct-up Sct-up Sct-up Sct-up Hold Hold Hold Hold Hold Nonc Nonc None Nonc Nonc Figure 2

Explanation / Answer

Clock edge 1:t=20ps;setup violation

Clock edge 2:t=60ps; setup violation

Clock edge 3:t=100ps; setup violation

Clock edge 4:t=140ps; setup violation

Clock edge 5:t=180ps; setup violation

Setup time is the time for which data should be made available before rising edge of clock,in this case it is 5ps.

Hold time is the minimum duration of clock pulse to hold data.

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