it 4 - ADIF in register ADCSRA: ADC Interrupt Flag is set when an ADC conversion

Question

it 4 - ADIF in register ADCSRA: ADC Interrupt Flag is set when an ADC

conversion completes and the Data Registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter- natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify- Write on ADCSRA, a pending interrupt can be disabled. Which of the following statements waits for ADC conversion to end?

while ((ADCSRA & (1 << ADIF)) != 0);

while ((ADCSRA & (1 << ADIF)) ==0);

while ((ADCSRA I (1 << ADIF)) != 0);

while ((ADCSRA I (1 << ADIF)) == 0);

while ((ADCSRA I (1 << ADIF)) != (1 << ADIF)) b.

In the above description of ADIF, which of the following statements sets ADIF bit to zero?

ADCSRA &= -(1 << ADIF);

ADCSRA I= (1 << ADIF);

ADCSRA &= (1 << ADIF);

ADCSRA I= -(1 << ADIF);

ADCSRA == -(1 << ADIF);

Explanation / Answer

Solution:-

Bit 4 - ADIF in register ADCSRA: ADC Interrupt Flag:-

while(ADCSRA & (1<<ADIF))==0

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