Write the VERILOG code for a 4-bit arithmetic/logic unit (ALU) which has as inpu
ID: 2293401 • Letter: W
Question
Write the VERILOG code for a 4-bit arithmetic/logic unit (ALU) which has as inputs two 4-bit vectors aluin a and aluin. b as well as a 1-bit carry in, Cin. The output is a 4-bit vector alu out. The ALU should operate on the inputs depending on the 4-bit control input C in the following table OPCODE Description Operation alu out alu in a + alu inb alu out alu in aalu in b Cin alu out- alu in a alu_in_b alu out -(alu ina & alu in_b) 0000 add 0001 add with Cin 0010 sub b from a 0011 Bit wise nand 0100 NOP 0101 Bit wise nor 0110NOP 0111bit wise inversion alu out alu in a alu outalu in a alu in b *NOP No Operation This will be compiled in modelsim and implemented on a FPGA Note you must interpret these operations based on Verilog syntax and directions given in the specification. In addition, 1. Cout should be the carry out (1 bit) 2. If arithmetic overflow occurs signal OF should be set to 1, otherwise it should be 0, since this makes no sense for logic operations Cout and OF should be set to O for thoseExplanation / Answer
module ALU (
input [3:0] alu_in_a, // input A
input [3:0] alu_in_b, // input B
input Cin, // Carry input
input [3:0] C, // selection line
output reg [3:0] alu_out, // output
output reg Cout, // Carry output flag
output reg OF // overflow flag
);
always @ (*)
begin
// for NOP operation and other combinations we are making outputs ZERO
alu_out = 32'd0;
Cout = 1'd0;
OF = 1'd0;
case(C)
4'b0000 : begin
{Cout, alu_out} = alu_in_a + alu_in_b;
OF = alu_in_a[3] ^ alu_in_b[3] ^ alu_out[3];
end
4'b0001 : begin
{Cout, alu_out} = alu_in_a + alu_in_b + Cin;
OF = alu_in_a[3] ^ alu_in_b[3] ^ alu_out[3] ^ Cin;
end
4'b0010 : begin
{Cout, alu_out} = alu_in_a - alu_in_b;
OF = alu_in_a[3] ^ alu_in_b[3] ^ alu_out[3] ;
end
4'b0011 : alu_out = ~(alu_in_a & alu_in_b) ;
4'b0011 : alu_out = ~(alu_in_a | alu_in_b) ;
4'b0111 : alu_out = ~(alu_in_a);
endcase
end
endmodule
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