This is in verilog!!! Design and test a 2-input multiplexer. Your circuit should

Question

This is in verilog!!!

Design and test a 2-input multiplexer. Your circuit should have three inputs: in0, inl and select; and a single output x. If select 0, then x should be the same as in0; if select 1, then x-inl. After writing the verilog for your multiplexer. develop a testplan: what combination of inputs will be sufficient to convince you that the circuit works correctly? Now design a testbench to apply these tests. Add Sdisplay statements as you like, compile and simulate your module, and observe the resulting waveforms. Confirm that your module works correctly.

Explanation / Answer

Verilog design

module mux21(
input in0,in1,select,
output x);

    assign x = select ?in1:in0;

endmodule

TestBench

module tb_mux21;

reg IN0,IN1,SEL;
wire Y;
  
mux21 MUX (.in0(IN0) ,.in1(IN1),.select(SEL),.x(Y));   
  
initial begin
IN0 =1'b0;
IN1= 1'b0;
SEL =1'b0;
#45 $finish;
end
  
always #6 IN0 =~IN0;
always #3 IN1 =~IN1;
always #5 SEL = ~SEL;
  
always @(Y)
$display( "time =%0t INPUT VALUES: IN0=%b IN1 =%b SEL =%b output value Y =%b ",$time,IN0,IN1,SEL,Y);

endmodule

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