Question 3 VHDL (25 marks) a) (5 marks) The entity for a full adder is given bel

Question

Question 3 VHDL (25 marks) a) (5 marks) The entity for a full adder is given below library IEEE; use IEEE.STD_LOGIC_ 1164.all; entity full adder is port (x, y, carry_in : in std_logic; sum, carry_out : out std_logic end full_adder; Write a corresponding architecture in behavioural VHDL using VHDL boolean functions. b) The entity for a 5 bit adder is given below: library IEEE; use IEEE. STD LOGIC 1164.all: entity add5 is port (x, y, : in std_logic_vector (4 downto 0); sum out std_logic_vector (4 downto 0) end add5; Where x, y and sum should be interpreted as signed binary numbers in two's complement notation i) (4 marks) Write a corresponding architecture for add5 in structural form using the "full_adder" from part a as the only component. Make sure that the architecture is purely structural (zero marks will be awarded for a behavioural description). Don't forget to declare "full_adder" as a component i) (2 marks) What range of decimal numbers can be represented by x, y and ii) (2 marks) Is the value on the sum output always valid? If not, under what iv) (2 marks) If the propagation delays of the full adder component are as sum conditions is it invalid? follows: From any input to the sum output From and input to the carry_out output: tpd-carry out - 1 ns tpd-sum 2 ns With the aid of a diagram, determine the worst case propagation delay for the "add5" implementation, from the x and y inputs to the sum output

Explanation / Answer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fab is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
s : out std_logic;
cr : out std_logic);
end fab;

architecture Behavioral of fab is

begin
process(a,b,c)
begin
if(a='0' and b='0' and c='0')then
s<='0';
cr<='0';
elsif( a='0' and b='0' and c='1')then
s<='1';
cr<='0';
elsif( a='0' and b='1' and c='0')then
s<='1';
cr<='0';
elsif( a='0' and b='1' and c='1')then
s<='0';
cr<='1';
elsif( a='1' and b='0' and c='0')then
s<='1';
cr<='0';
elsif( a='1' and b='0' and c='1')then
s<='0';
cr<='1';
elsif( a='1' and b='1' and c='0')then
s<='0';
cr<='1';
else
s<='1';
cr<='1';
end if;
end process;

end Behavioral;

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