PLEASE WRITE VERILOG CODE AND TESTBENCH ACCORDING TO WHATS GIVEN AND SHOW SIMULA
ID: 2294147 • Letter: P
Question
PLEASE WRITE VERILOG CODE AND TESTBENCH ACCORDING TO WHATS GIVEN AND SHOW SIMULATION WAVEFORM AS WELL!!
ASSERTED = 1(High) DEASSERTED = 0(Low)
Design an arbiter (FSM) in Verilog and test using Xilinx simulator. When only req_0 is asserted, gnt 0 is asserted. Similarly when only req 1 is asserted, gnt_1 is asserted and when only req_2 is asserted, gnt_2 is asserted. When both req_0 and req_1 are asserted then gnt_0 is asserted, otherwise when both req 1 and req_2 are asserted then gnt 1 is asserted. For all other combinations, gnt_2 will be asserted. The arbiter has three inputs and three outputs as shown in the diagram below. 2. Clock req 0 gnt 1 req 2 gnt 2 (a) Arbiter circuit The report should include the state diagrams, the Verilog codes and simulation waveforms for the design.Explanation / Answer
module arbiter ( input req_0, req_1, req_2, output reg gnt_0, gnt_1, gnt_2);
reg [2:0] pst,nst;
always@(posedge clk, negedge rst)
if(!rst) pst <= 3’d0;
else pst <= nst;
always@*
begin
if(!rst) nst = 3’d0;
else
case(pst)
default: case({req_0,req_1,req_2})
0: nst = 3’d0;
1: nst = 3’d1;
2: nst = 3’d2;
3: nst = 3’d3;
4: nst = 3’d4;
5: nst = 3’d5;
6: nst = 3’d6;
7: nst = 3’d7;
endcase
endcase
end
always@*
begin
if(!rst) { gnt_0, gnt_1, gnt_2} = 3’d0;
else
case(pst)
0 : {gnt_0, gnt_1, gnt_2} =3’d1;
1: {gnt_0, gnt_1, gnt_2} =3’d1;
2 : {gnt_0, gnt_1, gnt_2} =3’d2;
3 : {gnt_0, gnt_1, gnt_2} =3’d2;
4 : {gnt_0, gnt_1, gnt_2} =3’d4;
5 : {gnt_0, gnt_1, gnt_2} =3’d1;
6 : {gnt_0, gnt_1, gnt_2} =3’d4;
7 : {gnt_0, gnt_1, gnt_2} =3’d1;
Endcase
end
endmodule
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