Convert VHDL to Verilog library ieee; use ieee.std_logic_1164.all; use ieee.std_
ID: 2315457 • Letter: C
Question
Convert VHDL to Verilog
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity acc is
port(clk_acc: in std_logic;
rst_acc: in std_logic;
wr_acc: in std_logic;
input_acc: in std_logic_vector (7 downto 0);
output_acc: OUT std_logic_vector (7 downto 0));
end acc;
architecture acc of acc is
signal d:std_logic_vector(7 downto 0);
begin
process(rst_acc,wr_acc,clk_acc)
begin
if rst_acc='1' then
d<="00000000";
output_acc<="00000000";
elsif (clk_acc'event and clk_acc = '1') then
if wr_acc='1' then
d<=input_acc;
output_acc<=input_acc;
end if;
end if;
end process;
end acc;
Convert the VHDL code to Verilog
Explanation / Answer
module accu (in, acc, clk, reset);
input [7:0] in; input clk, reset; output [7:0] acc;
reg [7:0] acc;
always@(posedge clk) begin if(reset) acc<= 0;
else acc<=acc+in;
end
endmodule
// This is the testbench for our 8-bit accumulator
`timescale 1ns/10ps
module accu_tb;
reg clk, reset; reg [7:0] in;
wire [7:0] out;
accu accu1(in, out, clk, reset);
initial begin
clk =1'b0;
forever begin
#5 clk = ~clk;
end
end
initial begin
#50 $finish;
end
// Simulate the input signals
initial begin
#0 reset<=1;
in<=1; #5 reset<=0;
end
endmodule
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