(Question 2) (10 points) (a) Design a module in Verilog for a rising-edge clock

Question

(Question 2) (10 points) (a) Design a module in Verilog for a rising-edge clock triggered symchronous FSM che following schematic shows the appropriate inputs and outputs). The value of imput MOE drives the state transition below. If input RESET"-1, the FSM will switch to "STATE-000" at the next rising edge of clock. (5 points) of imput "MOVE MOVE RESET-, Fido t STATE CLK 0001 001 1 100 0 011 0 010 101 1 II synchronous reset module Fido (CLK, RESET, MOVE, STATE) input CLK, RESET, MOVE output reg [2:0] STATE always@L) begin else case (STATE) if STATE 3'b000: STATE 3 b001: STATE 3'b010: STATE 3 "b011 : STATE

Explanation / Answer

a)

module Fido(CLK,RESET,MOVE,STATE);

input CLK,RESET,MOVE;

output reg [2:0] STATE;

always @ (posedge CLK) begin

if (RESET) STATE <= 3’b000;

else case (STATE)

3’b000: STATE <= MOVE ? 3’b001 : 3’b000;

3’b001: STATE <= MOVE ? 3’b100 : 3’b010;

3’b010: STATE <= MOVE ? 3’b100 : 3’b011;

3’b011: STATE <= MOVE ? 3’b000 : 3’b011;

3’b100: STATE <= MOVE ? 3’b101 : 3’b111;

3’b101: STATE <= MOVE ? 3’b110 : 3’b011;

3’b110: STATE <= MOVE ? 3’b110 : 3’b111;

3’b111: STATE <= MOVE ? 3’b101 : 3’b001;

default: STATE <= 3’b000;

endcase

end

endmodule

Related Questions

Navigate

• Browse (All)
• Browse #
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.