vhdl code help me with my vhdl code! I was making the code about 4 bit multiplie

Question

vhdl code

help me with my vhdl code!

I was making the code about 4 bit multiplier so I made one and compiled but there was error.

<can't determine definition of operator ""<="" -- found 0 possible definition>

the code written below is what I made.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity multiplier is
port(A   : in std_logic_vector(3 downto 0);
   B   : in std_logic_vector(3 downto 0);
   P   : out std_logic_vector(7 downto 0));
end multiplier;

architecture behavior of multiplier is
signal pp0, pp1, pp2, pp3 : std_logic_vector(7 downto 0);
constant zero :std_logic_vector:="00000000";

begin
pp0 <= zero when B(0) = '0' else pp0(3 downto 0) <= A;
pp1 <= zero when B(1) = '0' else pp1(4 downto 1) <= A;
pp2 <= zero when B(2) = '0' else pp2(5 downto 2) <= A;
pp3 <= zero when B(3) = '0' else pp3(6 downto 3) <= A;
P <= pp0 + pp1 + pp2 + pp3;
end behavior;

I don't understand why this is not working. what is the problem??

Explanation / Answer

I think zero contant created is not working,either use zero directly or search for contant declaration in vhdl

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