Can someone write the following program in verilog. I am using Spartan 3E board.
ID: 2988017 • Letter: C
Question
Can someone write the following program in verilog. I am using Spartan 3E board.
Your top level design should have M0, M1, M2 and Cin inputs, three input switches SW1, SW2, SW3, and also clock input. The SW1 switch serves as asynchrouns reset signal. The SW2 switch and SW3 switch selects the follwoing operations:
(1). SW2 = 0, SW3=0, R[2] = M0 + (not M1) + Cin
(2). SW2 = 0, SW3=1, R[2] = M0 nand M1
(3). SW2 = 1, SW3=0, R[2] = M0 or M1
(4). SW2 = 1, SW3=1, R[2] = M0 xor M1.
Your internal hardware must include the following circuit.
Design your control to implement the above four results. Show your simulation demo.
I am using Xilinx Spartan 3E board to demo.
Explanation / Answer
************** CODE**************************
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:53:11 04/19/2014
// Design Name:
// Module Name: cheeg
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cheeg(
input M0,
input M1,
input M2,
input cin,
input [2:0]S,
// input SW2,
// input SW3,
input clk,
output F
);
reg [3:0]Y;
reg [3:0]R;
reg [3:0]W;
//reg [2:0]S;
reg [3:0]CE = "111";
reg [1:0]sel= "10";
reg clr,b,a;
always @ ( R[3] or M0 or M1 or M2 or W[0] or W[1] or W[2])
begin
Y[0] = (W[0]) ? R[3] : M0;
Y[1] = (W[1]) ? R[3] : M1;
Y[2] = (W[2]) ? R[3] : M2;
end
always @(posedge clk)
begin
if(CE[0])
begin
R[0] <= Y[0];
end
else if(clr)
begin
R[0] <= 0;
end
end
always @(posedge clk)
begin
if(CE[1]) begin
R[1] <= Y[1];
end else if(clr)
begin
R[0] <= 0;
end
end
always @(posedge clk)
begin
if(CE[2])
begin
R[2] <= Y[2];
end
else if(clr)
begin
R[0] <= 0;
end
end
//mux Design
always @ (R[0] or R[0] or R[0] or sel[0] or sel[1])
begin
if(sel[1])
begin
if(sel[0]) begin
b <= 0;
end else begin
b <= R[2];
end
end
else if(sel[0]) begin
b <= R[1];
end else begin
b <= R[0];
end
end
//ALU Design
always @(a or b or cin or S)
begin
case (S)
000 : Y[3] <= R[3] || b || cin ;
001 : Y[3] <= R[3] || ~(b) || cin ;
010 : Y[3] <= b ;
011 : Y[3] <= R[3]&&(~(b)) ;
100 : Y[3] <= R[3]&&b ;
101 : Y[3] <= R[3] || b;
110 : Y[3] <= ~(R[3]) ;
111 : Y[3] <= R[3] ^ b ;
endcase
end
assign f= Y[3];
// d flip flop
always @(posedge clk)
begin
if(CE[3]) begin
R[3] = Y[3];
end else if(clr) begin
R[3] <= 0;
end else
R[3] <= R[3];
end
endmodule
*********************************** Test Bench***********************************
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:36:23 04/20/2014
// Design Name: cheeg
// Module Name: F:/14.5/LearnVerilog/testbench_cheeg.v
// Project Name: LearnVerilog
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cheeg
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench_cheeg;
// Inputs
reg M0;
reg M1;
reg M2;
reg cin;
reg [2:0] S;
reg clk;
// Outputs
wire F;
// Instantiate the Unit Under Test (UUT)
cheeg uut (
.M0(M0),
.M1(M1),
.M2(M2),
.cin(cin),
.S(S),
.clk(clk),
.F(F)
);
initial begin
// Initialize Inputs
M0 = 0;
M1 = 0;
M2 = 0;
cin = 0;
S = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#20;
M0 = 1;
M1 = 1;
M2 = 1;
cin = 1;
S = "000";
#20;
M0 = 0;
M1 = 1;
M2 = 0;
cin = 0;
S = "001";
#20;
M0 = 1;
M1 = 0;
M2 = 1;
cin = 1;
S = "010";
#20;
M0 = 0;
M1 = 1;
M2 = 1;
cin = 0;
S = "011";
#20;
M0 = 1;
M1 = 1;
M2 = 0;
cin = 1;
S = "100";
#20;
M0 = 1;
M1 = 1;
M2 = 1;
cin = 0;
S = "101";
#20;
M0 = 1;
M1 = 1;
M2 = 1;
cin = 1;
S = "110";
#20;
M0 = 1;
M1 = 1;
M2 = 1;
cin = 0;
S = "111";
#20;
M0 = 1;
M1 = 1;
M2 = 1;
cin = 1;
S = "000";
#20;
M0 = 0;
M1 = 1;
M2 = 0;
cin = 0;
S = "001";
#20;
M0 = 1;
M1 = 0;
M2 = 1;
cin = 1;
S = "010";
#20;
M0 = 0;
M1 = 1;
M2 = 1;
cin = 0;
S = "011";
#20;
M0 = 1;
M1 = 1;
M2 = 0;
cin = 1;
S = "100";
#20;
M0 = 1;
M1 = 1;
M2 = 1;
cin = 0;
S = "101";
#20;
M0 = 1;
M1 = 1;
M2 = 1;
cin = 1;
S = "110";
#20;
M0 = 1;
M1 = 1;
M2 = 1;
cin = 0;
S = "111";
// Add stimulus here
end
always begin
#10 clk= ~clk;
end
endmodule
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