1) Write a counter model with the clock input clk of type bit, and an output q o
ID: 2989701 • Letter: 1
Question
1) Write a counter model with the clock input clk of type bit, and an output q of type integer. Behavioral architecture body must contain a process which declares a count variable initialized to zero. Process must wait for changes on clk. When clk changes to '1', the process must increment the count and assign its value to the output port.
2) Write model that represents a simple ALU with interger inputs and output, and a function select input of type bit. if the function select is '0', the ALU output should be the sum of th einputs; otherwise the output should be the difference of the inputs
Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
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entity BitAdder3 is
Port ( OPA : in integer;
OPB : in integer;
RESULT : out integer;
AS_SEL: in std_logic);
end BitAdder3;
architecture Behavioral of BitAdder3 is
signal Data_Add: integer;
signal Data_Sub: integer;
begin
Data_Add<=OPA+OPB;
Data_Sub<=OPA-OPB;
RESULT <= Data_Add when (AS_SEL = '1') else Data_Sub;
end Behavioral;
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